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    Method of making an integrated circuit bipolar memory cell
    1.
    发明授权
    Method of making an integrated circuit bipolar memory cell 失效
    制造集成电路双极存储单元的方法

    公开(公告)号：US4488350A

    公开(公告)日：1984-12-18

    申请号：US315678

    申请日：1981-10-27

    申请人： Madhukar B. Vora ,  William H. Herndon

    发明人： Madhukar B. Vora ,  William H. Herndon

    IPC分类号： H01L29/73 ,  G11C11/411 ,  H01L21/331 ,  H01L21/8229 ,  H01L27/06 ,  H01L27/102 ,  H01L21/225

    CPC分类号： H01L27/1025 ,  G11C11/4113 ,  H01L27/0688

    摘要： A static bipolar random access memory cell includes first and second transistors formed in epitaxial silicon pockets 41 and 42 in a substrate. The collectors 19 and 19' and bases 15 and 15' of the transistors are interconnected with polycrystalline silicon 21 doped to match the conductivity types of the regions contacted. Undesired PN junctions 40 and 40' created thereby are shorted using an overlying layer of a metal silicide 25. In a region overlying the N conductivity type polycrystalline silicon 23 or 23', the metal silicide is removed and a PN junction 37 or 37' created by depositing P conductivity type polycrystalline silicon 35c or 35c'. If desired additional P type polycrystalline silicon 35a and 35b may be deposited across the surface of the epitaxial layer where the base regions of the two transistors are formed to reduce the base series resistance.

    摘要翻译： 静态双极性随机存取存储单元包括在衬底中的外延硅袋41和42中形成的第一和第二晶体管。 晶体管的集电极19和19'以及基极15和15'与被掺杂以与所接触的区域的导电类型相匹配的多晶硅21互连。 由此产生的不期望的PN结40和40'使用金属硅化物25的上覆层短路。在覆盖N导电型多晶硅23或23'的区域中，去除金属硅化物并产生PN结37或37' 通过沉积P导电型多晶硅35c或35c'。 如果需要，可以在形成两个晶体管的基极区域的外延层的表面上沉积另外的P型多晶硅35a和35b以降低基极串联电阻。

    Integrated circuit bipolar memory cell
    2.
    发明授权
    Integrated circuit bipolar memory cell 失效
    集成电路双极存储单元

    公开(公告)号：US4622575A

    公开(公告)日：1986-11-11

    申请号：US647315

    申请日：1984-09-04

    申请人： Madhukar B. Vora ,  William H. Herndon

    发明人： Madhukar B. Vora ,  William H. Herndon

    IPC分类号： G11C11/411 ,  H01L27/06 ,  H01L27/102 ,  H01L29/04 ,  H01L27/02 ,  H01L29/70

    CPC分类号： H01L27/0688 ,  G11C11/4113 ,  H01L27/1025 ,  Y10S257/914

    摘要： A static bipolar random access memory cell includes first and second transistors formed in epitaxial silicon pockets 41 and 42 in a substrate. The collectors 19 and 19' and bases 15 and 15' of the transistors are interconnected with polycrystalline silicon 21 doped to match the conductivity types of the regions contacted. Undesired PN junctions 40 and 40' created thereby are shorted using an overlying layer of a metal silicide 25. In a region overlying the N conductivity type polycrystalline silicon 23 or 23', the metal silicide is removed and a PH junction 37 or 37' created by depositing P conductivity type polycrystalline silicon 35c or 35c'. If desired additional P type polycrystalline silicon 35a and 35b may be deposited across the surface of the epitaxial layer where the base regions of the two transistors are formed to reduce the base series resistance.

    摘要翻译： 静态双极性随机存取存储单元包括在衬底中的外延硅袋41和42中形成的第一和第二晶体管。 晶体管的集电极19和19'以及基极15和15'与被掺杂以与所接触的区域的导电类型相匹配的多晶硅21互连。 由此产生的不希望的PN结40和40'使用金属硅化物25的覆盖层而短路。在覆盖N导电型多晶硅23或23'的区域中，去除金属硅化物并产生PH结37或37' 通过沉积P导电型多晶硅35c或35c'。 如果需要，可以在形成两个晶体管的基极区域的外延层的表面上沉积另外的P型多晶硅35a和35b以降低基极串联电阻。

    BIPMOS decoder circuit
    3.
    发明授权
    BIPMOS decoder circuit 失效
    BIPMOS解码电路

    公开(公告)号：US4857772A

    公开(公告)日：1989-08-15

    申请号：US42995

    申请日：1987-04-27

    申请人： William H. Herndon

    发明人： William H. Herndon

    IPC分类号： H03M7/00 ,  G11C8/10

    CPC分类号： G11C8/10

    摘要： A decoder incorporates the advantageous features of both bipolar and BICMOS decoding circuits through the use of BIPMOS technology. PMOS gating transistors are used to control the operation of bipolar output transistors. It is only necessary to operate the PMOS transistors with relatively small drain voltage variations, since the bipolar transistors are sensitive to such small variations. Further, transient signals are referenced to one power supply voltage only, to thereby make the logic swing and performance characteristics of the decoder independent of power supply voltage variations. Therefore it becomes possible to use PMOS transistors that have smaller voltage requirements than conventional CMOS circuits.

    Bias voltage distribution system
    4.
    发明授权
    Bias voltage distribution system 失效
    偏压配电系统

    公开(公告)号：US5506541A

    公开(公告)日：1996-04-09

    申请号：US416531

    申请日：1995-04-03

    申请人： William H. Herndon

    发明人： William H. Herndon

    IPC分类号： G05F3/24 ,  H03K19/00 ,  H03K19/086 ,  G05F1/10

    CPC分类号： G05F3/24

    摘要： A bias generation and distribution system in which bias potentials are generated at one main location within a logic circuit and then distributed throughout the logic circuit to MOS load devices, MOS load networks, other bias voltage conversion centers, and logic circuits is disclosed. The system generates a first bias voltage that provides a temperature compensated voltage that is utilized to bias MOS load devices and parallel MOS load networks. The first bias voltage generator includes either a reference MOS load device or a reference parallel MOS load network which determines the value of the first bias voltage. The reference MOS load network includes a switching network responsive to a first set of control signals. The first set of control signals may be adjusted to vary the value of the first bias voltage to compensate for process variations. The first bias voltage is distributed to either remote single load MOS devices or to remote parallel MOS load networks. The remote load networks also include switching networks responsive to a second set of control signals. The second set of control signals may be varied to determine the resistivity of the remote MOS load networks depending on the value of the first bias voltage. The system also generates a second temperature compensated bias voltage that is utilized along with the first bias voltage to bias remote bias conversion circuits. The remote conversion circuits generate a third bias voltage that is utilized, along with the first bias voltage, to bias remote logic gates. The first bias voltage biases the MOS resistive load of the logic gate and the third bias voltage biases the MOS current device of the logic gate. The second bias voltage generator and the remote conversion circuits are implemented with controllable switching networks so that current and logic swing adjustments of the logic gate may be performed.

    摘要翻译： 一种偏置发生和分配系统，其中在逻辑电路内的一个主要位置处产生偏置电位，然后在整个逻辑电路中分配到MOS负载器件，MOS负载网络，其他偏置电压转换中心和逻辑电路。 该系统产生第一偏置电压，其提供用于偏置MOS负载装置和并联MOS负载网络的温度补偿电压。 第一偏置电压发生器包括参考MOS负载装置或参考并联MOS负载网络，其确定第一偏置电压的值。 参考MOS负载网络包括响应于第一组控制信号的交换网络。 可以调整第一组控制信号以改变第一偏置电压的值以补偿过程变化。 第一个偏置电压分配到远程单负载MOS器件或远程并行MOS负载网络。 远程负载网络​​还包括响应于第二组控制信号的交换网络。 可以改变第二组控制信号以根据第一偏置电压的值确定远程MOS负载网络的电阻率。 该系统还产生第二温度补偿偏置电压，其与第一偏置电压一起使用以偏置远程偏置转换电路。 远程转换电路产生与第一偏置电压一起被利用以偏置远程逻辑门的第三偏置电压。 第一偏置电压偏置逻辑门的MOS电阻负载，第三偏置电压偏置逻辑门的MOS电流器件。 第二偏置电压发生器和远程转换电路由可控开关网络实现，从而可以执行逻辑门的电流和逻辑摆幅调整。

    Bimos circuit that provides low power dissipation and high transient drive capability
    6.
    发明授权
    Bimos circuit that provides low power dissipation and high transient drive capability 失效
    Bimos电路提供低功耗和高瞬态驱动能力

    公开(公告)号：US4868421A

    公开(公告)日：1989-09-19

    申请号：US17634

    申请日：1987-02-24

    申请人： William H. Herndon ,  Robert J. Proebsting

    发明人： William H. Herndon ,  Robert J. Proebsting

    IPC分类号： H03K19/00 ,  H03K19/086 ,  H03K19/0944

    CPC分类号： H03K19/09448 ,  H03K19/0008 ,  H03K19/086

    摘要： To reduce the total power dissipation of an emitter-follower driver or logic circuit, an MOS transistor is connected between an output terminal of the circuit and a suitable voltage source. The MOS transistor is operated in opposite phase to an emitter follower bipolar transistor that provides driving current to the output terminal, so that one is on while the other is off. The MOS transistor limits the current in the emitter follower transistor in either state of the circuit, thus reducing power dissipation. It also provides for a larger transient driving current to the output terminal, thus increasing the switching speed of the circuit.

    摘要翻译： 为了降低发射极跟随器驱动器或逻辑电路的总功耗，MOS晶体管连接在电路的输出端和合适的电压源之间。 MOS晶体管工作在与输出端子提供驱动电流的发射极跟随双极晶体管的相反相位上，使得一个导通，而另一个截止。 MOS晶体管限制了电路中任一状态下的射极跟随器晶体管中的电流，从而降低功耗。 它还为输出端提供更大的瞬态驱动电流，从而提高电路的开关速度。

    Memory cell power scavenging apparatus and method
    7.
    发明授权
    Memory cell power scavenging apparatus and method 失效
    记忆体功率清除装置及方法

    公开(公告)号：US4627034A

    公开(公告)日：1986-12-02

    申请号：US669929

    申请日：1984-11-09

    申请人： William H. Herndon

    发明人： William H. Herndon

    IPC分类号： G11C5/14 ,  G11C8/08 ,  G11C11/41 ,  G11C11/414 ,  G11C13/00

    CPC分类号： G11C5/14 ,  G11C11/414 ,  G11C8/08

    摘要： The present invention utilizes the power available for application to a static RAM cell in a manner which provides efficient use of the power so that greater standby power may be applied to the static RAM to increase the memory speed. The current required to maintain the memory cell in a preset state flows from the U.sub.cc source through a row of parallel memory cells and through a common bias supply and various peripheral circuits, such as decoders. A shunt voltage regulator controls the dependence of the common bias supply voltage on current fluctuations caused by addressing and deaddressing the memory cells. The invention includes an isolation device for isolating a particular row of memory cells when it is addressed without disturbing the bias on other memory cell rows. Similarly, the reference voltages of each of the peripheral circuits can be made independent of the common bias supply voltage and independent of the other peripheral circuits by the use of a local voltage regulator on each peripheral.

    摘要翻译： 本发明以提供有效利用电力的方式利用可用于静态RAM单元的功率，使得可以将更大的待机功率施加到静态RAM以增加存储器速度。 将存储单元保持在预设状态所需的电流从Ucc源流经一行并行存储单元并通过公共偏置电源和诸如解码器的各种外围电路流动。 分流电压调节器控制公共偏置电源电压对由存储器单元的寻址和死锁引起的电流波动的依赖性。 本发明包括隔离装置，用于当寻址存储器单元的特定行时隔离特定行，而不干扰其它存储单元行的偏置。 类似地，每个外围电路的参考电压可以独立于公共偏置电源电压，并且通过在每个外围设备上使用本地电压调节器而与其它外围电路无关。

    Bit line powered translinear memory cell
    8.
    发明授权
    Bit line powered translinear memory cell 失效
    位线供电的直流存储单元

    公开(公告)号：US4442509A

    公开(公告)日：1984-04-10

    申请号：US315679

    申请日：1981-10-27

    申请人： William H. Herndon

    发明人： William H. Herndon

    IPC分类号： G11C11/411 ,  G11C13/00

    CPC分类号： G11C11/4116

    摘要： A bit line powered translinear memory cell includes a pair of NPN transistors Q101 and Q102 having cross-coupled bases and collectors. Diode loads D101 and D102 couple the NPN transistors Q101 and Q102 to the bit lines 301 and 302. The emitters of the two transistors Q101 and Q102 are coupled together and to a word line 103. Cell parasitic capacitances C101 and C102 are used to maintain data in nonaddressed memory cells during reading of other cells coupled to the same word line 103.

    摘要翻译： 位线供电的跨线存储器单元包括具有交叉耦合基极和集电极的一对NPN晶体管Q101和Q102。 二极管负载D101和D102将NPN晶体管Q101和Q102耦合到位线301和302.两个晶体管Q101和Q102的发射极耦合在一起并连接到字线103.单元寄生电容C101和C102用于维持数据 在读取耦合到同一字线103的其它单元的非寻址存储单元中。

    Switched impedance emitter coupled logic gate
    9.
    发明授权
    Switched impedance emitter coupled logic gate 失效
    开关阻抗发射极耦合逻辑门

    公开(公告)号：US4713560A

    公开(公告)日：1987-12-15

    申请号：US871639

    申请日：1986-06-05

    申请人： William H. Herndon

    发明人： William H. Herndon

    IPC分类号： H03K19/00 ,  H03K19/086 ,  H03K3/01 ,  H03K17/60 ,  H03K19/02

    CPC分类号： H03K19/086 ,  H03K19/0016

    摘要： There is disclosed herein an ECL gate using switchable load impedance means to allow the gate to be placed in a low power-consumption mode while preserving the logic state existing at the outputs of the gate at the time it is switched into the low-power mode. N-channel or P-channel MOS transistors are used as the switchable load impedances. The gates of these transistors are coupled to a MODE control signal which causes the MOS transistors to switch between high-impedance and low-impedance states. Another MOS transistor having its gate coupled to the same MODE control signal is used as the current source for the bias current to the conventional ECL current mirror. When low-power mode operation is desired, all the MOS transistors are switched to their high-impedance states. This reduces the bias current flowing through the ECL gate, thereby reducing its power consumption. The logic states at the output nodes are preserved by virtue of the load impedance of the ECL switching transistors having increased simultaneously with their collector currents having decreased.

    摘要翻译： 这里公开了一种使用可切换负载阻抗装置的ECL门，以允许栅极被置于低功耗模式，同时保持门切换到低功率模式时在门的输出处存在的逻辑状态 。 N沟道或P沟道MOS晶体管用作可切换负载阻抗。 这些晶体管的栅极耦合到使得MOS晶体管在高阻抗和低阻抗状态之间切换的MODE控制信号。 将其栅极耦合到相同的MODE控制信号的另一MOS晶体管用作用于传统ECL电流镜的偏置电流的电流源。 当需要低功耗模式操作时，所有MOS晶体管都切换到高阻态。 这减少了流过ECL门的偏置电流，从而降低其功耗。 由于ECL开关晶体管的负载阻抗与它们的集电极电流同时增加而减小，所以输出节点处的逻辑状态得以保留。

    Bypass circuit for word line cell discharge current
    10.
    发明授权
    Bypass circuit for word line cell discharge current 失效
    用于字线电池放电电流的旁路电路

    公开(公告)号：US4488263A

    公开(公告)日：1984-12-11

    申请号：US363198

    申请日：1982-03-29

    申请人： William H. Herndon ,  Jonathan J. Stinehelfer

    发明人： William H. Herndon ,  Jonathan J. Stinehelfer

    IPC分类号： G11C11/414 ,  G11C11/415 ,  G11C11/40

    CPC分类号： G11C11/415

    摘要： A current bypass for a microelectric memory, such as a static RAM, diverts word line discharge current such that the current does not flow through the memory cells of a selected word line or along an upper word line conductor. In a first embodiment, the bypass comprises a resistor R1 (R2) and a diode D10 (D20) in series and coupled between an upper word line conductor 50 and word line discharge current source V.sub.CC, and a lower word line conductor 51 and word line discharge current sink 42. In another embodiment of the invention, a transistor Q10 (Q20) is used in lieu of the diode. By bypassing current from the upper word line conductor and word line memory cells, metal migration is eliminated and narrower metal lines may be used to form the word lines. By eliminating a flow of steady state discharge current through the memory cells, memory cell current saturation is eliminated.

    摘要翻译： 用于诸如静态RAM的微电存储器的电流旁路转移字线放电电流，使得电流不流过选定字线或沿着上字线导体的存储器单元。 在第一实施例中，旁路包括串联的电阻器R1（R2）和二极管D10（D20），并耦合在上字线导体50和字线放电电流源VCC之间，并且下字线导体51和字线 放电电流阱42.在本发明的另一个实施例中，使用晶体管Q10（Q20）代替二极管。 通过绕过上部字线导体和字线存储器单元的电流，消除了金属迁移，并且可以使用较窄的金属线来形成字线。 通过消除通过存储单元的稳态放电电流的流动，消除了存储单元电流饱和。