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    Non-self-aligned side channel implants for flash memory cells
    21.
    发明授权
    Non-self-aligned side channel implants for flash memory cells 失效
    用于闪存单元的非自对准侧通道植入物

    公开(公告)号：US6127222A

    公开(公告)日：2000-10-03

    申请号：US991687

    申请日：1997-12-16

    Applicant: Scott D. Luning ,  Mark Randolph

    Inventor： Scott D. Luning ,  Mark Randolph

    IPC: H01L21/336

    CPC classification number: H01L29/66825

    Abstract: A system and method for providing a flash memory cell on a semiconductor substrate are disclosed. The system and method include providing a side implant and providing an implant in at least one of a drain or a source of the flash memory cell.

    Abstract translation: 公开了一种用于在半导体衬底上提供闪存单元的系统和方法。 该系统和方法包括提供侧植入物并在闪速存储器单元的漏极或源极中的至少一个中提供植入物。

    Flash memory programming and verification with reduced leakage current
    24.
    发明授权
    Flash memory programming and verification with reduced leakage current 有权
    闪存编程和验证，减少漏电流

    公开(公告)号：US08031528B2

    公开(公告)日：2011-10-04

    申请号：US12557721

    申请日：2009-09-11

    Applicant: Ashot Melik-Martirosian ,  Ed Runnion ,  Mark Randolph ,  Meng Ding

    Inventor： Ashot Melik-Martirosian ,  Ed Runnion ,  Mark Randolph ,  Meng Ding

    IPC: G11C16/06 ,  G11C16/04

    CPC classification number: G11C16/0475 ,  G11C16/12 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459

    Abstract: A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are biased with a positive source bias voltage to reduce or eliminate leakage current that might otherwise conduct through the target memory cells. A positive source bias voltage may also be applied to target memory cells during verification operations (program verify, soft program verify, erase verify) to reduce or eliminate leakage current that might otherwise introduce errors in the verification operations.

    Abstract translation: 根据本发明的示例性实施例配置的闪存系统采用虚拟接地阵列架构。 在编程操作期间，目标存储器单元被偏置为正的源偏置电压，以减少或消除否则可能通过目标存储器单元传导的漏电流。 在验证操作（程序验证，软程序验证，擦除验证）期间，也可以将正源偏置电压施加到目标存储器单元，以减少或消除可能在验证操作中引入错误的泄漏电流。

    ELECTRONIC DEVICE HAVING A DOPED REGION WITH A GROUP 13 ATOM
    26.
    发明申请
    ELECTRONIC DEVICE HAVING A DOPED REGION WITH A GROUP 13 ATOM 审中-公开
    具有第13组ATOP的区域的电子设备

    公开(公告)号：US20090189212A1

    公开(公告)日：2009-07-30

    申请号：US12022795

    申请日：2008-01-30

    Applicant: Gwyn Robert Jones ,  Mark Randolph

    Inventor： Gwyn Robert Jones ,  Mark Randolph

    IPC: H01L29/792 ,  H01L21/336

    CPC classification number: H01L29/0847 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

    Abstract: An electronic device includes a memory cell. The memory cell includes a semiconductor region, a first current-carrying electrode adjacent to the semiconductor region, and a first dopant-containing region adjacent to a first current-carrying electrode. The semiconductor region includes a Group 14 atom and the first dopant-containing region includes a Group 13 atom. The Group 13 atom has an atomic number greater than the atomic number of the Group 14 atom.

    Abstract translation: 电子设备包括存储单元。 存储单元包括半导体区域，与半导体区域相邻的第一载流电极和与第一载流电极相邻的第一掺杂剂区域。 半导体区域包括第14族原子，第一掺杂剂区域包括第13族原子。 第13族原子的原子数大于第14族原子的原子数。

    HIGH K STACK FOR NON-VOLATILE MEMORY
    27.
    发明申请
    HIGH K STACK FOR NON-VOLATILE MEMORY 有权
    用于非易失性存储器的高K堆叠

    公开(公告)号：US20090155992A1

    公开(公告)日：2009-06-18

    申请号：US12351553

    申请日：2009-01-09

    Applicant: Wei ZHENG ,  Mark RANDOLPH ,  Hidehiko SHIRAIWA

    Inventor： Wei ZHENG ,  Mark RANDOLPH ,  Hidehiko SHIRAIWA

    IPC: H01L21/28

    CPC classification number: H01L29/792 ,  G11C16/0475 ,  H01L21/28273 ,  H01L21/28282

    Abstract: A memory device may include a source region and a drain region formed in a substrate and a channel region formed in the substrate between the source and drain regions. The memory device may further include a first oxide layer formed over the channel region, the first oxide layer having a first dielectric constant, and a charge storage layer formed upon the first oxide layer. The memory device may further include a second oxide layer formed upon the charge storage layer, a layer of dielectric material formed upon the second oxide layer, the dielectric material having a second dielectric constant that is greater than the first dielectric constant, and a gate electrode formed upon the layer of dielectric material.

    Abstract translation: 存储器件可以包括形成在衬底中的源极区域和漏极区域以及形成在源极和漏极区域之间的衬底中的沟道区域。 存储器件还可以包括形成在沟道区上的第一氧化物层，第一氧化物层具有第一介电常数，以及形成在第一氧化物层上的电荷存储层。 存储器件还可以包括形成在电荷存储层上的第二氧化物层，形成在第二氧化物层上的介电材料层，介电材料具有大于第一介电常数的第二介电常数，以及栅电极 形成在电介质材料层上。

    Methods and systems for reducing the threshold voltage distribution following a memory cell erase
    30.
    发明授权
    Methods and systems for reducing the threshold voltage distribution following a memory cell erase 有权
    减少存储单元擦除后阈值电压分布的方法和系统

    公开(公告)号：US07170796B1

    公开(公告)日：2007-01-30

    申请号：US11193391

    申请日：2005-08-01

    Applicant: Yi He ,  Gwyn Jones ,  Edward F. Runnion ,  Mark Randolph

    Inventor： Yi He ,  Gwyn Jones ,  Edward F. Runnion ,  Mark Randolph

    IPC: G11C11/34

    CPC classification number: G11C16/14 ,  G11C16/3468 ,  G11C16/3472 ,  G11C16/3477

    Abstract: A method is provided for erasing a memory device including a number of memory cells, the memory cells including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes erasing a group of memory cells to lower a maximum threshold voltage of the group of memory cells below a first predetermined level. The group of memory cells is soft-programmed to raise a minimum threshold voltage of the group of memory cells above a second predetermined level. The group of memory cells is erased, following soft-programming, resulting in a reduced threshold voltage distribution associated with the group of memory cells.

    Abstract translation: 提供了一种用于擦除包括多个存储单元的存储器件的方法，所述存储器单元包括衬底，控制栅极，电荷存储元件，源极区域和漏极区域。 该方法包括擦除一组存储器单元以将存储器单元组的最大阈值电压降低到低于第一预定水平。 存储器单元组被软编程以将存储器单元组的最小阈值电压提高到高于第二预定水平。 在软编程之后，存储单元组被擦除，导致与该组存储器单元相关联的阈值电压分布降低。

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