公开(公告)号：US20100261045A1

公开(公告)日：2010-10-14

申请号：US12386034

申请日：2009-04-13

申请人： Wen-Sung Wu ,  Meng-Chang Liu ,  Shen-Yuan Chien

发明人： Wen-Sung Wu ,  Meng-Chang Liu ,  Shen-Yuan Chien

IPC分类号： H01M2/10 ,  H01R13/46

CPC分类号： H01R11/287 ,  H01M2/20 ,  H01M2/202 ,  H01M2/30 ,  H01R11/282

摘要： Methods and apparatus supporting an electrical connection are disclosed. Systems previously equipped with wire interfaces, such as battery terminals, can be equipped with a connector assembly to significantly reduce a hazard of electrical shock to a user. The connector assembly includes a stress relief component that attenuates a force, applied to the stress relief component, to reduce its effect on the connector assembly. By attenuating the force, the connector assembly maintains a substantially fixed position relative to the battery pack component and mitigates a potential for disruption in electrical connectivity. Techniques disclosed herein benefit users of battery packs or other devices as well as manufacturers by increasing safety, reliability, and ergonomics.

摘要翻译： 公开了支持电连接的方法和装置。 先前配备有线接口的系统（例如电池端子）可以配备有连接器组件，以显着减少对用户的电击的危险。 连接器组件包括应力消除部件，其减弱施加到应力消除部件上的力，以减小其对连接器组件的影响。 通过衰减力，连接器组件相对于电池组件保持基本上固定的位置，并减轻了电气连接中断的可能性。 本文所公开的技术通过提高安全性，可靠性和人体工程学而使电池组或其它设备以及制造商的用户受益。

公开(公告)号：USD615037S1

公开(公告)日：2010-05-04

申请号：US29345100

申请日：2009-10-09

申请人： Meng-Chang Liu ,  Kyle Brookshire ,  Karl D. Langmuir

设计人： Meng-Chang Liu ,  Kyle Brookshire ,  Karl D. Langmuir

公开(公告)号：USD606937S1

公开(公告)日：2009-12-29

申请号：US29334541

申请日：2009-03-27

申请人： Kyle Brookshire ,  Meng-Chang Liu

设计人： Kyle Brookshire ,  Meng-Chang Liu

公开(公告)号：US06875705B2

公开(公告)日：2005-04-05

申请号：US10235193

申请日：2002-09-04

申请人： Chao-Jie Tsai ,  Jeng Yang Pan ,  Chin-Nan Wu ,  Meng-Chang Liu ,  Su-Yu Yeh

发明人： Chao-Jie Tsai ,  Jeng Yang Pan ,  Chin-Nan Wu ,  Meng-Chang Liu ,  Su-Yu Yeh

IPC分类号： H01L21/285 ,  H01L21/302 ,  H01L21/3213 ,  H01L21/461

CPC分类号： H01L21/32134 ,  H01L21/28518

摘要： A method for forming salicides with lower sheet resistance and increased sheet resistance uniformity over a semiconductor process wafer including providing a semiconductor process wafer having exposed silicon containing areas at a process surface; depositing a metal layer including at least one of cobalt and titanium over the process surface; carrying out at least one thermal annealing process to react the metal layer and silicon to form a metal silicide over the silicon containing areas; and, wet etching unsilicided areas of the metal layer with a wet etching solution including phosphoric acid (H3PO4), nitric acid (HNO3), and a carboxylic acid to leave salicides covering silicon containing areas at the process surface.

摘要翻译： 一种用于在半导体工艺晶片上形成具有较低的薄层电阻和增加的薄层电阻均匀性的硫化物的方法，包括提供在处理表面具有暴露的含硅区域的半导体工艺晶片; 在工艺表面上沉积包括钴和钛中的至少一种的金属层; 执行至少一个热退火工艺以使金属层和硅反应以在含硅区域上形成金属硅化物; 并用含有磷酸（H 3 PO 4），硝酸（HNO 3）和羧酸的湿蚀刻溶液湿法蚀刻金属层的无硅区域，以留下在工艺表面覆盖含硅区域的水杨酸盐。

公开(公告)号：US06284642B1

公开(公告)日：2001-09-04

申请号：US09372077

申请日：1999-08-11

申请人： Meng-Chang Liu ,  Chao-Bao Cheng ,  Kuo-Chin Hsu

发明人： Meng-Chang Liu ,  Chao-Bao Cheng ,  Kuo-Chin Hsu

IPC分类号： H01L214763

CPC分类号： H01L21/76813

摘要： A new process is provided to create openings and interconnect patterns for the dual damascene structure. Four layers of dielectric are sequentially deposited over a pattern of interconnect metal. The via hole pattern is defined, the interconnect line pattern is next defined. The via pattern is etched though the upper layer of dielectric and through the stop layer. Only one etch processing step is used to create the desired vias and the desired interconnect line pattern. After the interconnect patterns and vias have been created in the four layers of dielectric, a barrier layer is blanket deposited, the metal is deposited for the dual damascene structure and the interconnect line pattern and polished.

摘要翻译： 提供了一种新工艺来创建双镶嵌结构的开口和互连图案。 在互连金属的图案上顺序地沉积四层电介质。 通孔图案被定义，下一个定义了互连线图案。 通孔图案通过电介质的上层并通过阻挡层进行蚀刻。 仅使用一个蚀刻处理步骤来产生期望的通孔和期望的互连线图案。 在四层电介质中形成了互连图形和通孔之后，屏蔽层被覆盖沉积，金属被沉积用于双镶嵌结构和互连线图案并被抛光。

公开(公告)号：US6040223A

公开(公告)日：2000-03-21

申请号：US373636

申请日：1999-08-13

申请人： Meng-Chang Liu ,  Jyh-Feng Lin ,  Ming-Shu Yen ,  Su-Ying Su ,  Fu-Ying Chiu ,  Chien-Hung Lin

发明人： Meng-Chang Liu ,  Jyh-Feng Lin ,  Ming-Shu Yen ,  Su-Ying Su ,  Fu-Ying Chiu ,  Chien-Hung Lin

IPC分类号： H01L21/336 ,  H01L21/60 ,  H01L21/768

CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L29/6656 ,  H01L29/6659

摘要： A method for making improved polysilicon FET gate electrodes having composite sidewall spacers is achieved. After forming the polysilicon gate electrodes on the substrate, a SiO.sub.2 stress-release layer is deposited having a trapezoidal shape. A Si.sub.3 N.sub.4 layer is deposited and plasma etched back using the SiO.sub.2 layer as an etch-endpoint-detect layer to form composite sidewall spacers that include portions of the trapezoidal-shaped oxide layer. The SiO.sub.2 layer protects the source/drain areas from plasma etch damage that could cause high leakage currents. The Si.sub.3 N.sub.4 also extends over the SiO.sub.2 layer at the upper edges of the polysilicon gate electrodes. This prevents erosion of the SiO.sub.2 along the gate electrodes when the remaining oxide is removed from the source/drain areas using hydrofluoric acid wet etching. When an insulating layer is deposited over the FETs, and self-aligned contact openings are etched to the source/drain areas and extending over the gate electrodes, the Si.sub.3 N.sub.4 extending over the portion of the trapezoidal-shaped SiO.sub.2 layer that forms part of the composite sidewall spacer protects the SiO.sub.2 from etching. This results in more reliable contacts without degrading the FET performance.

摘要翻译： 实现了具有复合侧壁间隔物的改进的多晶硅FET栅电极的方法。 在基板上形成多晶硅栅电极之后，沉积具有梯形形状的SiO 2应力释放层。 沉积Si 3 N 4层并使用SiO 2层等离子体蚀刻回蚀刻端点检测层，以形成包括梯形氧化物层的部分的复合侧壁间隔物。 SiO 2层保护源极/漏极区域免受可能导致高漏电流的等离子体蚀刻损伤。 Si 3 N 4也在多晶硅栅电极的上边缘处在SiO 2层上延伸。 当使用氢氟酸湿蚀刻从剩余的氧化物从源极/漏极区域移除时，这防止了沿着栅电极的SiO 2的侵蚀。 当绝缘层沉积在FET上方，并且自对准接触开口被蚀刻到源极/漏极区域并且在栅电极上延伸时，Si3N4延伸超过形成复合材料的一部分的梯形SiO 2层的部分 侧壁间隔件保护SiO 2免受蚀刻。 这导致更可靠的触点，而不会降低FET性能。

公开(公告)号：US5801094A

公开(公告)日：1998-09-01

申请号：US873500

申请日：1997-06-12

申请人： Tri-Rung Yew ,  Meng-Chang Liu ,  Water Lur ,  Shih-Wei Sun

发明人： Tri-Rung Yew ,  Meng-Chang Liu ,  Water Lur ,  Shih-Wei Sun

IPC分类号： H01L21/768 ,  H01L21/28

CPC分类号： H01L21/7681 ,  H01L21/76804

摘要： A dual damascene process forms a two level metal interconnect structure by first providing a interlayer oxide over a device structure and covering the interlevel oxide layer with an etch stop layer. The etch stop layer is patterned to form openings corresponding to the pattern of the interconnects that are to be formed in the first level of the two level interconnect structure. After the etch stop layer is patterned, an intermetal oxide layer is provided over the etch stop layer. Because the etch stop layer is relatively thin, the topography formed on the surface of the intermetal oxide layer is relatively small. A photoresist mask is then provided over the intermetal oxide layer with openings in the mask exposing portions of the intermetal oxide layer in the pattern of the wiring lines to be provided in the second level of the interconnect structure. The intermetal oxide layer is etched and the etching process continues to form openings in the interlayer oxide where the interlayer oxide is exposed by the openings in the etch stop layer. Thus, in a single etching step, the openings for both the second level wiring lines and the first level interconnects are defined. Metal is then deposited over the structure and excess metal is removed by chemical mechanical polishing to define the two level interconnect structure.

摘要翻译： 双镶嵌工艺通过首先在器件结构上提供层间氧化物并用蚀刻停止层覆盖层间氧化物层，形成两层金属互连结构。 蚀刻停止层被图案化以形成对应于将要形成在两层互连结构的第一层中的互连图案的开口。 在蚀刻停止层被图案化之后，在蚀刻停止层上方提供金属间氧化物层。 因为蚀刻停止层相对较薄，所以形成在金属间氧化物层的表面上的形貌相对较小。 然后在金属间氧化物层之上提供光致抗蚀剂掩模，其中掩模中的开口在布线的图案中的金属间氧化物层的暴露部分中设置有互连结构的第二层。 蚀刻金属间氧化物层，并且蚀刻工艺继续在层间氧化物中形成开口，其中层间氧化物被蚀刻停止层中的开口暴露。 因此，在单个蚀刻步骤中，限定了用于二级布线和第一级互连的开口。 然后将金属沉积在结构上，通过化学机械抛光除去多余的金属以限定两层互连结构。

公开(公告)号：US08852784B2

公开(公告)日：2014-10-07

申请号：US12386034

申请日：2009-04-13

申请人： Wen-Sung Wu ,  Meng-Chang Liu ,  Shen-Yuan Chien

发明人： Wen-Sung Wu ,  Meng-Chang Liu ,  Shen-Yuan Chien

IPC分类号： H01M2/20 ,  H01M2/30 ,  H01R11/28

CPC分类号： H01R11/287 ,  H01M2/20 ,  H01M2/202 ,  H01M2/30 ,  H01R11/282

摘要： Methods and apparatus supporting an electrical connection are disclosed. Systems previously equipped with wire interfaces, such as battery terminals, can be equipped with a connector assembly to significantly reduce a hazard of electrical shock to a user. The connector assembly includes a stress relief component that attenuates a force, applied to the stress relief component, to reduce its effect on the connector assembly. By attenuating the force, the connector assembly maintains a substantially fixed position relative to the battery pack component and mitigates a potential for disruption in electrical connectivity. Techniques disclosed herein benefit users of battery packs or other devices as well as manufacturers by increasing safety, reliability, and ergonomics.

摘要翻译： 公开了支持电连接的方法和装置。 先前配备有线接口的系统（例如电池端子）可以配备有连接器组件，以显着减少对用户的电击的危险。 连接器组件包括应力消除部件，其减弱施加到应力消除部件上的力，以减小其对连接器组件的影响。 通过衰减力，连接器组件相对于电池组件保持基本上固定的位置，并减轻了电气连接中断的可能性。 本文所公开的技术通过提高安全性，可靠性和人体工程学而使电池组或其它设备以及制造商的用户受益。

公开(公告)号：US20140009837A1

公开(公告)日：2014-01-09

申请号：US13542881

申请日：2012-07-06

申请人： Meng-Chang Liu ,  Meng-Jia Hsiao

发明人： Meng-Chang Liu ,  Meng-Jia Hsiao

IPC分类号： G02B5/02 ,  B29C65/48

CPC分类号： G09F9/30 ,  G09F13/0409

摘要： A method for providing a supporting structure in a flat-plate display is disclosed. The display has a display panel, a diffuser panel, a reflector panel to reflect light from a backlight unit towards the diffuser panel in order to illuminate the display panel. The supporting structure has a plurality of support pins located in that gap between the diffuser panel and the reflector panel for supporting the diffuser panel. The support pins are either molded with the diffuser panel, fused into the diffuser panel or attached to the diffuser panel using an index matching optical adhesive.

摘要翻译： 公开了一种在平板显示器中提供支撑结构的方法。 显示器具有显示面板，扩散板，反射板，用于将来自背光单元的光反射到扩散板以照亮显示面板。 所述支撑结构具有多个支撑销，所述支撑销位于所述扩散板与所述反射板之间的所述间隙中，用于支撑所述扩散板。 支撑销或者用扩散板模制，熔化到扩散板中，或者使用折射率匹配的光学粘合剂附着在扩散板上。

公开(公告)号：US08510614B2

公开(公告)日：2013-08-13

申请号：US12487773

申请日：2009-06-19

申请人： Meng-Chang Liu ,  Pin-Chou Liu

发明人： Meng-Chang Liu ,  Pin-Chou Liu

IPC分类号： G11C29/00

CPC分类号： G06F11/006

摘要： A bad block identification method for a memory is provided. The memory includes at least one memory block for storing data. A data decoding function is performed on the data, and it is determined whether the data decoding function was performed successfully. If the data decoding function was not performed successfully, at least one predetermined location in the memory block is checked. It is determined whether the predetermined location is marked by predetermined information. If the predetermined location is not marked by the predetermined information, the memory block is identified as a bad block.

摘要翻译： 提供了一种用于存储器的坏块识别方法。 存储器包括用于存储数据的至少一个存储块。 对数据执行数据解码功能，确定数据解码功能是否成功执行。 如果数据解码功能未成功执行，则检查存储器块中的至少一个预定位置。 确定预定位置是否被预定信息标记。 如果预定位置未被预定信息标记，则存储块被识别为坏块。