公开(公告)号：US08072238B1

公开(公告)日：2011-12-06

申请号：US12883297

申请日：2010-09-16

Applicant: Michael D. Hutton

Inventor： Michael D. Hutton

IPC: H03K19/177 ,  H03K17/62

CPC classification number: H03K19/17736 ,  H03K19/17728

Abstract: A high efficiency PLD architecture having logic elements that can be selectively combined to perform higher order logic functions than can be performed alone by a single logic element. The programmable logic device includes a logic block having a first logic element. The first logic element includes a first pair of sub-function generators and is capable of implementing logic functions of a first order. The logic block also includes a second logic element having a second pair of sub-function generators. A programmable sharing circuitry is also included in the logic block. The programmable sharing circuitry selectively couples the first pair of sub-function generators and the second pair of sub-function generators so that the first logic element is capable of performing logic functions of either (i) the first order, or (ii) a second order. The second order is higher than the first order.

Abstract translation: 具有逻辑元件的高效率PLD架构，其可以被选择性地组合以执行比单个逻辑元件单独执行的更高阶逻辑功能。 可编程逻辑器件包括具有第一逻辑元件的逻辑块。 第一逻辑元件包括第一对子功能发生器，并且能够实现一阶的逻辑功能。 逻辑块还包括具有第二对子功能发生器的第二逻辑元件。 逻辑块中也包括可编程共享电路。 可编程共享电路选择性地耦合第一对子功能发生器和第二对子功能发生器，使得第一逻辑元件能够执行（i）第一阶或（ii）第二逻辑单元的逻辑功能， 订购。 第二个订单高于第一个订单。

公开(公告)号：US07890910B1

公开(公告)日：2011-02-15

申请号：US11499451

申请日：2006-08-04

Applicant: Michael D. Hutton ,  Gregg William Baeckler ,  Jinyong Yuan ,  Chris Wysocki ,  Pouyan Djahani

Inventor： Michael D. Hutton ,  Gregg William Baeckler ,  Jinyong Yuan ,  Chris Wysocki ,  Pouyan Djahani

IPC: G06F17/50

CPC classification number: H03K19/173 ,  H03K19/1736 ,  H03K19/17728

Abstract: A programmable logic device architecture having logic elements with dedicated hardware to configure the look up tables of the logic element to either perform logic functions or to operate as a register for pipelining or other purposes. The programmable logic device includes a general interconnect and a plurality of logic array blocks interconnected by the general interconnect. Each of the plurality of logic blocks further includes one or more logic elements. The logic elements each include a first look up table, a second look up table, and dedicated hardware within the logic element to configure the first look table and the second look up table as a register without having to use the general interconnect. In one embodiment, the dedicated hardware includes a plurality of dedicated interconnects within the logic element to configure the two look up tables as a pair of cross coupled muxes or latches when configured as a register.

Abstract translation: 具有逻辑元件的可编程逻辑器件结构具有专用硬件以配置逻辑元件的查找表以执行逻辑功能或作为流水线或其它目的的寄存器来操作。 可编程逻辑器件包括通用互连和通过一般互连互连的多个逻辑阵列块。 多个逻辑块中的每一个还包括一个或多个逻辑元件。 逻辑元件各自包括第一查询表，第二查询表和逻辑元件内的专用硬件，以将第一查询表和第二查询表配置为寄存器而不必使用通用互连。 在一个实施例中，专用硬件包括逻辑元件内的多个专用互连，以在配置为寄存器时将两个查找表配置为一对交叉耦合的多路复用器或锁存器。

公开(公告)号：US07839165B2

公开(公告)日：2010-11-23

申请号：US12577061

申请日：2009-10-09

Applicant: Michael D. Hutton ,  Andy L. Lee

Inventor： Michael D. Hutton ,  Andy L. Lee

IPC: H03K19/173

CPC classification number: H03K19/17748 ,  H03K19/17784

Abstract: A programmable logic device (PLD) includes a configuration circuit, and first and second freeze-logic circuits. The configuration circuit provides configuration data for configuring programmable resources of the PLD during a configuration mode of the PLD. One of the two freeze-logic circuits provides a freeze logic signal during the configuration mode of the PLD. The other freeze-logic circuit provides a freeze logic signal during a user mode of the PLD.

Abstract translation: 可编程逻辑器件（PLD）包括配置电路以及第一和第二冻结逻辑电路。 配置电路提供用于在PLD的配置模式期间配置PLD的可编程资源的配置数据。 两个冻结逻辑电路之一在PLD的配置模式期间提供冻结逻辑信号。 另一个冻结逻辑电路在PLD的用户模式期间提供冻结逻辑信号。

公开(公告)号：US07804325B1

公开(公告)日：2010-09-28

申请号：US12148877

申请日：2008-04-22

Applicant: Erhard Joachim Pistorius ,  Michael D. Hutton

Inventor： Erhard Joachim Pistorius ,  Michael D. Hutton

IPC: H03K19/173

CPC classification number: H03K19/177

Abstract: To improve interfacing between a block of dedicated function circuitry and blocks of more general purpose circuitry on an integrated circuit (“IC”), signals that are to be output by the dedicated function block are routed internally in that block so that they go into interconnection circuitry on the IC for more efficient application by that interconnection circuitry to the general purpose circuitry. Some of this routing internal to the dedicated function block may be controllably variable. The routing internal to the dedicated function block may also be arranged to take advantage of “sneak” connections that may exist between the dedicated function block and the general purpose blocks.

Abstract translation: 为了改善专用功能电路块与集成电路（“IC”）上更通用电路的块之间的接口，由专用功能块输出的信号在该块内部被路由到它们进入互连 IC上的电路，用于将该互连电路更有效地应用于通用电路。 专用功能块内部的一些路由可能是可控的。 专用功能块内部的路由也可以被布置为利用可能存在于专用功能块和通用块之间的“潜行”连接。

公开(公告)号：US07724032B2

公开(公告)日：2010-05-25

申请号：US11894283

申请日：2007-08-20

Applicant: Michael D. Hutton ,  James G. Schleicher, II ,  Daniel R. Mansur

Inventor： Michael D. Hutton ,  James G. Schleicher, II ,  Daniel R. Mansur

IPC: H03K19/177

CPC classification number: H03K19/17744 ,  H03K19/17732 ,  H03K19/17796

Abstract: A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a “custom region” and an “interface region.” The custom region can implement the custom or semi-custom ASIC design and the interface region can integrate and connect the custom region to the rest of the FPGA circuitry. The custom region may be based on a structured ASIC design. The interface region may allow the ASIC fabric to be incorporated within the hierarchical organization of the FPGA, allowing the custom region to connect to the FPGA circuitry in a seamless manner.

Abstract translation: 提供了具有集成专用集成电路（“ASIC”）结构的现场可编程门阵列（“FPGA”）。 ASIC结构可以用于在FPGA内实现一个或多个定制或半定制硬块。 ASIC结构可以由“自定义区域”和“接口区域”组成。自定义区域可以实现定制或半定制ASIC设计，接口区域可以将自定义区域集成并连接到FPGA的其余部分 电路。 定制区域可以基于结构化ASIC设计。 接口区域可以允许将ASIC结构并入FPGA的分层组织中，从而允许定制区域以无缝的方式连接到FPGA电路。

公开(公告)号：US07705628B1

公开(公告)日：2010-04-27

申请号：US11486164

申请日：2006-07-12

Applicant: Michael D. Hutton ,  Andy L. Lee ,  Gregg William Baeckler ,  Jinyong Yuan ,  Keith Duwel

Inventor： Michael D. Hutton ,  Andy L. Lee ,  Gregg William Baeckler ,  Jinyong Yuan ,  Keith Duwel

IPC: G06F7/38 ,  H03K19/173 ,  H03K19/177 ,  H03K19/094 ,  H01L25/00

CPC classification number: H03K19/173 ,  H03K19/1736 ,  H03K19/17728

Abstract: A programmable logic device architecture having logic elements with dedicated hardware to configure the look up tables of the logic element to either perform logic functions or to operate as a register for pipelining or other purposes. The programmable logic device includes a general interconnect and a plurality of logic array blocks interconnected by the general interconnect. Each of the plurality of logic blocks further includes one or more logic elements. The logic elements each include a first look up table, a second look up table, and dedicated hardware within the logic element to configure the first look table and the second look up table as a register without having to use the general interconnect. In one embodiment, the dedicated hardware includes a plurality of dedicated interconnects within the logic element to configure the two look up tables as a pair of cross coupled muxes or latches when configured as a register.

Abstract translation: 具有逻辑元件的可编程逻辑器件结构具有专用硬件以配置逻辑元件的查找表以执行逻辑功能或作为流水线或其它目的的寄存器来操作。 可编程逻辑器件包括通用互连和通过一般互连互连的多个逻辑阵列块。 多个逻辑块中的每一个还包括一个或多个逻辑元件。 逻辑元件各自包括第一查询表，第二查询表和逻辑元件内的专用硬件，以将第一查询表和第二查询表配置为寄存器而不必使用通用互连。 在一个实施例中，专用硬件包括逻辑元件内的多个专用互连，以在配置为寄存器时将两个查找表配置为一对交叉耦合的多路复用器或锁存器。

公开(公告)号：US07577929B1

公开(公告)日：2009-08-18

申请号：US11187722

申请日：2005-07-21

Applicant: Michael D. Hutton ,  David Karchmer

Inventor： Michael D. Hutton ,  David Karchmer

IPC: G06F17/50 ,  G06F9/45 ,  H03K17/693

CPC classification number: G06F17/5036 ,  G06F17/5031

Abstract: A performance estimation module estimates the performance values of user designs in early phases of compilation and accounts for the performance variability introduced by subsequent compilation phases. The user design is parameterized. The performance estimation model outputs a probability distribution function of estimated performance values of the user design, based upon this parameterization. The performance estimation model is created by parameterizing sample designs. The sample designs are compiled and analyzed to determine their performance values. To account for random variability in compilation phases, the module compiles and analyzes sample designs multiple times. The performance estimation model is created from the relationship between sample designs' performance values and their parameterizations. A regression analysis may be used to determine this relationship. The performance estimation model can be updated with the analysis of compiled user designs. The performance values can include timing, power, and resource consumption.

Abstract translation: 性能估计模块在编译的早期阶段估计用户设计的性能价值，并考虑随后编译阶段引入的性能变异性。 用户设计参数化。 基于该参数化，性能估计模型输出用户设计的估计性能值的概率分布函数。 通过参数化样本设计创建性能估计模型。 样本设计被编译和分析以确定其性能值。 为了解决编译阶段的随机变化，模块多次对样本进行编译和分析。 性能估计模型是根据样本设计的性能值与参数化之间的关系来创建的。 可以使用回归分析来确定这种关系。 可以通过编译用户设计的分析来更新性能估计模型。 性能值可以包括时序，功率和资源消耗。

公开(公告)号：US07337100B1

公开(公告)日：2008-02-26

申请号：US10461921

申请日：2003-06-12

Applicant: Michael D. Hutton ,  Joachim Pistorius ,  Babette van Antwerpen ,  Gregg Baeckler ,  Richard Yuan ,  Yean-Yow Hwang

Inventor： Michael D. Hutton ,  Joachim Pistorius ,  Babette van Antwerpen ,  Gregg Baeckler ,  Richard Yuan ,  Yean-Yow Hwang

IPC: G06F17/50 ,  G06F9/455 ,  G01R31/28

CPC classification number: G06F17/5068

Abstract: A multiple-pass synthesis technique improves the performance of a design. In a specific embodiment, synthesis is performed in two or more passes. In a first pass, a first synthesis is performed, and in a second or subsequent pass, a second synthesis or resynthesis is performed. During the first synthesis, the logic will be mapped to for example, the logic structures (e.g., logic elements, LUTs, synthesis gates) of the target technology such as a programmable logic device. Alternatively a netlist may be provided from a third party. Before the second synthesis, a fast or abbreviated fit may be performed of the netlist to a specific device (e.g., specific programmable logic device product). Before the second synthesis, the netlist obtained from the first synthesis (or provided by a third party) is unmapped and then the second synthesis is performed. Since a partial fit is performed, the second synthesis has more visibility and optimize the logic better than by using a single synthesis pass. After the second synthesis pass, a more detailed fit is performed.

Abstract translation: 多通道合成技术提高了设计的性能。 在具体实施方案中，以两次或更多次通过进行合成。 在第一次通过中，执行第一次合成，并且在第二次或随后的过程中进行第二次合成或再合成。 在第一合成期间，逻辑将被映射到例如目标技术的逻辑结构（例如，逻辑元件，LUT，合成门），诸如可编程逻辑器件。 或者，可以从第三方提供网表。 在第二合成之前，可以将网表快速或缩写配合到特定设备（例如，特定的可编程逻辑设备产品）。 在第二次合成之前，从第一次合成（或由第三方提供）获得的网表被未映射，然后进行第二次合成。 由于执行部分拟合，所以第二合成比通过使用单个合成通路更好的可见性和优化逻辑。 在第二次合成之后，进行更详细的拟合。

公开(公告)号：US07176718B1

公开(公告)日：2007-02-13

申请号：US11040457

申请日：2005-01-21

Applicant: Michael D Hutton ,  Bruce Pedersen ,  Sinan Kaptanoglu ,  David Lewis ,  Tim Vanderhoek

Inventor： Michael D Hutton ,  Bruce Pedersen ,  Sinan Kaptanoglu ,  David Lewis ,  Tim Vanderhoek

IPC: H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/17728

Abstract: A programmable logic element grouping for use in multiple instances on a programmable logic device includes more than the traditional number of logic elements sharing secondary signal (e.g., clock, clock enable, clear, etc.) selection circuitry. The logic elements in such a grouping are divided into at least two subgroups. Programmable interconnection circuitry is provided for selectively applying signals from outside the grouping and signals fed back from the logic elements in the grouping to primary inputs of the logic elements in the grouping. The programmable interconnection circuitry limits possible application of at least some of these signals to one or the other of the subgroups, and/or provides for possible application of at least some of these signals to a greater percentage of the primary inputs to one of the subgroups than to the other.

Abstract translation: 在可编程逻辑器件上的多个实例中使用的可编程逻辑元件组合包括多于共享次级信号（例如，时钟，时钟使能，清零等）选择电路的传统数量的逻辑元件。 这种分组中的逻辑元素被划分为至少两个子组。 提供了可编程互连电路，用于选择性地将分组外的信号和分组中的逻辑元件反馈的信号分组中的逻辑元件的主要输入。 可编程互连电路将这些信号中的至少一些信号的可能应用限制到子组中的一个或另一个，并且/或提供这些信号中的至少一些信号到其中一个子组的较大百分比的主要输入的可能应用 比对方。

公开(公告)号：US07135888B1

公开(公告)日：2006-11-14

申请号：US10897770

申请日：2004-07-22

Applicant: Michael D. Hutton ,  David Lewis

Inventor： Michael D. Hutton ,  David Lewis

IPC: H03K19/177 ,  H01L25/00 ,  G06F7/38

CPC classification number: H01L27/11898 ,  H01L27/0207 ,  H03K19/17744

Abstract: Techniques are provided for routing signals to and from input/output pads on a programmable chip that reduce signal delay times. A programmable routing structure is provided that is dedicated to routing signals to and from the input/output (I/O) pads. The programmable routing structure can include long conductors that transmit signals across the chip quickly without the delay encountered in shorter routing conductors. Signals can be routed to and from the I/O pads through vertical and horizontal dedicated routing conductors that bypass global routing conductors. The dedicated I/O routing structure allows signals to be driven onto the chip and off chip more quickly can be achieved through standard programmable routing structures. The dedicated I/O routing structure can be depopulated to reduce the number of programmable connections between the individual conductors, decreasing die area requirements.

Abstract translation: 提供技术用于将信号路由到可编程芯片上的输入/输出焊盘上，以减少信号延迟时间。 提供了可编程路由结构，其专用于将信号路由到输入/输出（I / O）焊盘。 可编程路由结构可以包括长导体，其在芯片上快速传输信号，而不会在较短路由导体中遇到延迟。 信号可以通过垂直和水平专用路由导线从I / O焊盘传送，从而绕过全局布线导线。 专用I / O路由结构允许通过标准可编程路由结构实现信号更快地驱动到芯片和芯片上。 可以减少专用I / O路由结构，以减少单个导体之间的可编程连接数量，从而减少管芯面积要求。