公开(公告)号：US20100322009A1

公开(公告)日：2010-12-23

申请号：US12817665

申请日：2010-06-17

申请人： Takeshi SHIMANE ,  Naoyuki Shigyo ,  Mutsuo Morikado

发明人： Takeshi SHIMANE ,  Naoyuki Shigyo ,  Mutsuo Morikado

IPC分类号： G11C16/04 ,  H01L29/792

CPC分类号： H01L27/11568 ,  G11C16/0483 ,  G11C16/10

摘要： According to one embodiment, a semiconductor memory device includes a semiconductor substrate, memory cells without a source region and a drain region, and a first insulating film. The memory cells are arranged adjacent to one another on the semiconductor substrate and include a first gate electrode including a charge accumulation layer. A current path functioning as a source region or a drain region of a selected memory cell is formed in the semiconductor substrate when a voltage is applied to the first gate electrode of one of unselected memory cells. The first insulating film is formed on the semiconductor substrate to fill a region between the first gate electrodes of the memory cells adjacent to each other.

摘要翻译： 根据一个实施例，半导体存储器件包括半导体衬底，没有源极区和漏极区的存储单元和第一绝缘膜。 存储单元在半导体衬底上彼此相邻地布置，并且包括包括电荷累积层的第一栅电极。 当向未选择的存储单元之一的第一栅电极施加电压时，在半导体衬底中形成用作所选存储单元的源极区或漏极区的电流路径。 第一绝缘膜形成在半导体衬底上以填充彼此相邻的存储单元的第一栅电极之间的区域。

公开(公告)号：US20080201682A1

公开(公告)日：2008-08-21

申请号：US12081431

申请日：2008-04-16

申请人： Naoyuki Shigyo ,  Tetsuya Yamaguchi

发明人： Naoyuki Shigyo ,  Tetsuya Yamaguchi

IPC分类号： G06F17/50

CPC分类号： H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of designing a wiring structure of an LSI is capable of reducing a capacitance variation ratio ΔC/C or a resistance-by-capacitance variation ratio Δ(RC)/(RC) of the wiring structure. The method sets a process-originated variation ratio (∈P) for the wiring structure, a tolerance (ξC) for the capacitance variation ratio (ΔC/C), and a tolerance (ξRC) for the resistance-by-capacitance variation ratio (Δ(RC)/(RC)), evaluates a fringe capacitance ratio (F=CF/CP) according to a fringe capacitance CF and parallel-plate capacitance CP of the wiring structure, and determines the wiring structure so that the fringe capacitance ratio (F) may satisfy the following: For    Δ   C C  ≤ ξ C ,  F ≥ δ P ξ C - 1 ( 1 ) For    Δ  ( RC ) RC  ≤ ξ RC ,  F ≤ ( 1 - δ P )  δ P δ P - ξ RC - 1 ( 2 ) The method employs an equivalent-variations condition defined as |ΔC/C|=|Δ(RC)/(RC)| to determine the shape parameters of each wire of the wiring structure.

公开(公告)号：US20060125023A1

公开(公告)日：2006-06-15

申请号：US11291436

申请日：2005-11-30

申请人： Naoyuki Shigyo ,  Kentaro Watanabe

发明人： Naoyuki Shigyo ,  Kentaro Watanabe

IPC分类号： H01L29/76

CPC分类号： H01L29/665 ,  H01L27/0266 ,  H01L29/0653 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/7833 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes first, second, third, and fourth semiconductor regions, a gate electrode, and silicide layers. The first, second, and third semiconductor regions are formed in a semiconductor substrate while being spaced part from each other. The fourth semiconductor region is formed in the semiconductor substrate between the second semiconductor region and the third semiconductor region and has an electric resistance higher than the first, second, and third semiconductor regions. In a direction perpendicular to a direction to connect the first and second semiconductor regions, the fourth semiconductor region has a width smaller than that of the semiconductor substrate sandwiched between the first semiconductor region and the second semiconductor region. The gate electrode is formed above the semiconductor substrate between the first semiconductor region and the second semiconductor region. The silicide layer is formed on each of the first, second, third semiconductor regions and the gate electrode.

摘要翻译： 半导体器件包括第一，第二，第三和第四半导体区域，栅电极和硅化物层。 第一，第二和第三半导体区域形成在半导体衬底中，同时彼此间隔开。 第四半导体区域形成在第二半导体区域和第三半导体区域之间的半导体衬底中，并且具有高于第一，第二和第三半导体区域的电阻。 在垂直于连接第一和第二半导体区域的方向的方向上，第四半导体区域的宽度小于夹在第一半导体区域和第二半导体区域之间的半导体衬底的宽度。 栅极电极形成在第一半导体区域和第二半导体区域之间的半导体衬底之上。 硅化物层形成在第一，第二，第三半导体区域和栅电极中的每一个上。

公开(公告)号：US06978434B1

公开(公告)日：2005-12-20

申请号：US09602253

申请日：2000-06-23

申请人： Naoyuki Shigyo ,  Tetsuya Yamaguchi

发明人： Naoyuki Shigyo ,  Tetsuya Yamaguchi

IPC分类号： H01L21/3205 ,  G06F17/50 ,  H01L21/82 ,  H01L23/522 ,  H01L29/06 ,  H03K19/003

CPC分类号： H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： A wiring structure of a semiconductor device, includes a wiring layer formed on an insulating film, a width (W) of each wire in the wiring layer and a thickness (H) of the insulating film satisfying “W/H

摘要翻译： 半导体器件的布线结构包括形成在绝缘膜上的布线层，布线层中的布线的宽度（W）和绝缘膜的厚度（H）满足“W / H <1”的长度 布线层中的各布线的长度（L）等于或大于1mm。

公开(公告)号：US5698869A

公开(公告)日：1997-12-16

申请号：US527515

申请日：1995-09-13

申请人： Makoto Yoshimi ,  Satoshi Inaba ,  Atsushi Murakoshi ,  Mamoru Terauchi ,  Naoyuki Shigyo ,  Yoshiaki Matsushita ,  Masami Aoki ,  Takeshi Hamamoto ,  Yutaka Ishibashi ,  Tohru Ozaki ,  Hitomi Kawaguchiya ,  Kazuya Matsuzawa ,  Osamu Arisumi ,  Akira Nishiyama

发明人： Makoto Yoshimi ,  Satoshi Inaba ,  Atsushi Murakoshi ,  Mamoru Terauchi ,  Naoyuki Shigyo ,  Yoshiaki Matsushita ,  Masami Aoki ,  Takeshi Hamamoto ,  Yutaka Ishibashi ,  Tohru Ozaki ,  Hitomi Kawaguchiya ,  Kazuya Matsuzawa ,  Osamu Arisumi ,  Akira Nishiyama

IPC分类号： H01L21/336 ,  H01L27/12 ,  H01L29/786 ,  H01L31/072

CPC分类号： H01L29/66666 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78618 ,  H01L29/78681

摘要： A structure of a semiconductor device and a method of manufacturing the same is provided wherein a leakage current can be reduced while improving a drain breakdown voltage of an Insulated-Gate transistor such as a MOSFET, MOSSIT and a MISFET, and a holding characteristic of a memory cell such as a DRAM using these transistors as switching transistors can be improved, and further a reliability of a gate oxide film in a transfer gate can be improved. More particularly, a narrow band gap semiconductor region such as Si.sub.x Ge.sub.1-x, Si.sub.x Sn.sub.1-x, PbS is formed in an interior of a source region or a drain region in the SOI.IG-device. By selecting location and/or mole fraction of the narrow band gap semiconductor region in a SOI film, or selecting a kind of impurity element to compensate the crystal lattice mismatching due to the narrow-bandgap semiconductor region, the generation of crystal defects can be suppressed. Further the structure that the influences of the crystal defects to the transistor or memory characteristics such as the leakage current can be suppressed, even if the crystal defects are generated, are also proposed.

摘要翻译： 提供半导体器件的结构及其制造方法，其中可以减小漏电流，同时改善诸如MOSFET，MOSSIT和MISFET的绝缘栅晶体管的漏极击穿电压，以及保持特性 可以提高诸如使用这些晶体管的DRAM作为开关晶体管的存储单元，并且还可以提高传输栅极中的栅极氧化膜的可靠性。 更具体地，在SOI.IG器件中的源极区域或漏极区域的内部形成诸如SixGe1-x，SixSn1-x，PbS的窄带隙半导体区域。 通过选择SOI膜中的窄带隙半导体区域的位置和/或摩尔分数，或者选择一种杂质元素来补偿由于窄带隙半导体区域引起的晶格失配，可以抑制晶体缺陷的产生 。 此外，即使产生晶体缺陷，也可以抑制晶体缺陷对晶体管的影响或漏电流等存储特性的结构。

公开(公告)号：US5254867A

公开(公告)日：1993-10-19

申请号：US726764

申请日：1991-07-08

申请人： Sanae Fukuda ,  Naoyuki Shigyo

发明人： Sanae Fukuda ,  Naoyuki Shigyo

IPC分类号： H01L21/28 ,  H01L29/423 ,  H01L29/51 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/4232 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

摘要： A MOSFET comprises a silicon substrate 1 having a source/drain region 7b formed in a surface region thereof, an insulating film 3 formed of silicon oxide, and a gate electrode 4a. The side surface region of the electrode 4a is covered with an insulating film 6 formed of silicon nitride. The insulating film 6 has an extended portion interposed between the electrode 4a and the insulating film 3 in a manner to surround the lower corner portion 4b of the electrode. Since the insulating film 6 has a dielectric constant larger than that of the insulating film 3, it is possible to suppress the electric field intensity at the lower corner portion 4b of the electrode.

摘要翻译： MOSFET包括在其表面区域中形成有源极/漏极区域7b的硅衬底1，由氧化硅形成的绝缘膜3和栅极电极4a。 电极4a的侧面区域由氮化硅形成的绝缘膜6覆盖。 绝缘膜6具有以包围电极的下角部4b的方式介于电极4a和绝缘膜3之间的延伸部分。 由于绝缘膜6的介电常数大于绝缘膜3的介电常数，因此能够抑制电极的下角部4b的电场强度。