公开(公告)号：US09036409B2

公开(公告)日：2015-05-19

申请号：US14336600

申请日：2014-07-21

Applicant: Ovonyx, Inc.

Inventor： George A. Gordon ,  Semyon D. Savransky ,  Ward D. Parkinson ,  Sergey Kostylev ,  James Reed ,  Tyler A. Lowrey ,  Ilya V. Karpov ,  Gianpaolo Spadini

IPC: G11C11/00 ,  G11C13/00 ,  G11C8/10 ,  G11C11/56 ,  G11C16/34 ,  G11C29/04

CPC classification number: G11C13/0033 ,  G11C8/10 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/003 ,  G11C13/0035 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C16/3431 ,  G11C29/04 ,  G11C2013/0052 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/76

Abstract: Disturb from the reset to the set state may be reduced by creating an amorphous phase that is substantially free of crystal nuclei when programming the reset state in a phase change memory. In some embodiments, this can be achieved by using a current or a voltage to program that exceeds the threshold voltage of the phase change memory element, but does not exceed a safe current voltage which would cause a disturb.

公开(公告)号：US20040228163A1

公开(公告)日：2004-11-18

申请号：US10782737

申请日：2004-02-18

Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

Inventor： Osama Khouri ,  Claudio Resta

IPC: G11C011/00

CPC classification number: G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2213/79

Abstract: A phase change memory has an array formed by a plurality of cells, each including a memory element of calcogenic material and a selection element connected in series to the memory element; a plurality of address lines connected to the cells; a write stage and a reading stage connected to the array. The write stage is formed by current generators, which supply preset currents to the selected cells so as to modify the resistance of the memory element. Reading takes place in voltage, by appropriately biasing the selected cell and comparing the current flowing therein with a reference value.

Abstract translation: 相变存储器具有由多个单元形成的阵列，每个单元包括煅烧材料的存储元件和与存储元件串联连接的选择元件; 连接到所述单元的多个地址线; 连接到阵列的写阶段和阅读阶段。 写入级由电流发生器形成，电流发生器向所选择的单元提供预设电流，以便改变存储元件的电阻。 读取通过适当地偏置所选择的单元并将其中流动的电流与参考值进行比较来进行电压。

公开(公告)号：US20030223285A1

公开(公告)日：2003-12-04

申请号：US10331185

申请日：2002-12-27

Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

Inventor： Osama Khouri ,  Ferdinando Bedeschi

IPC: G11C029/00

CPC classification number: G11C13/0026 ,  G11C7/22 ,  G11C13/0038 ,  G11C16/24 ,  G11C2216/22

Abstract: A nonvolatile memory device is described comprising a memory array, a row decoder and a column selector for addressing the memory cells of the memory array, and a biasing stage for biasing the array access device terminal of the addressed memory cell. The biasing stage is arranged between the column selector and the memory array and comprises a biasing transistor having a drain terminal connected to the column selector, a source terminal connected to the array access device terminal of the addressed memory cell, and a gate terminal receiving a logic driving signal, the logic levels of which are defined by precise and stable voltages and are generated by a logic block and an output buffer cascaded together. The output buffer may be supplied with either a read voltage or a program voltage supplied by a multiplexer. The biasing transistor may be either included as part of the column selector and formed by the selection transistor which is closest to the addressed memory cell or distinct from the selection transistors of the column selector.

Abstract translation: 描述了一种非易失性存储器件，其包括用于寻址存储器阵列的存储单元的存储器阵列，行解码器和列选择器，以及用于偏置寻址的存储器单元的阵列存取器件端子的偏置级。 偏置级布置在列选择器和存储器阵列之间，并且包括偏置晶体管，漏极端子连接到列选择器，源极端子连接到寻址存储单元的阵列存取器件端子，栅极端子接收 逻辑驱动信号，其逻辑电平由精确和稳定的电压定义，并由逻辑块和输出缓冲器一起级联产生。 可以向输出缓冲器提供由多路复用器提供的读取电压或编程电压。 偏置晶体管可以被包括为列选择器的一部分，并且由选择晶体管形成，该选择晶体管最靠近寻址的存储单元或与列选择器的选择晶体管不同。

公开(公告)号：US20030219924A1

公开(公告)日：2003-11-27

申请号：US10313991

申请日：2002-12-05

Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

Inventor： Roberto Bez ,  Fabio Pellizzer ,  Caterina Riva ,  Romina Zonca

IPC: H01L021/06 ,  H01L021/4763

CPC classification number: G11C13/0004 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691 ,  Y10S438/947

Abstract: A contact structure, including a first conducting region having a first thin portion with a first sublithographic dimension in a first direction; a second conducting region having a second thin portion with a second sublithographic dimension in a second direction transverse to said first direction; the first and second thin portions being in direct electrical contact and defining a contact area having a sublithographic extension. The thin portions are obtained using deposition instead of lithography: the first thin portion is deposed on a wall of an opening in a first dielectric layer; the second thin portion is obtained by deposing a sacrificial region on vertical wall of a first delimitation layer, deposing a second delimitation layer on the free side of the sacrificial region, removing the sacrificial region to form a sublithographic opening that is used to etch a mold opening in a mold layer and filling the mold opening.

Abstract translation: 一种接触结构，包括：第一导电区域，具有在第一方向上具有第一亚光刻尺寸的第一薄部分; 第二导电区域，具有第二薄部分，具有横向于所述第一方向的第二方向的第二亚光刻尺寸; 第一和第二薄部分直接电接触并且限定具有亚光刻延伸部的接触区域。 使用沉积代替光刻获得薄部分：第一薄部分被放置在第一介电层中的开口的壁上; 通过在第一限定层的垂直壁上去除牺牲区域，在牺牲区域的自由侧上取代第二限定层，去除牺牲区域以形成用于蚀刻模具的亚光刻开口来获得第二薄部分 在模具层中开口并填充模具开口。