公开(公告)号：US5432120A

公开(公告)日：1995-07-11

申请号：US154551

申请日：1993-11-19

Applicant: Thomas Meister ,  Reinhard Stengl

Inventor： Thomas Meister ,  Reinhard Stengl

IPC: C30B25/04 ,  C30B33/12 ,  H01L21/20 ,  H01L21/205 ,  H01L21/331 ,  H01L21/336

CPC classification number: H01L29/66287 ,  C30B25/04 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L29/66651

Abstract: For producing a laterally limited, single-crystal region on a substrate, for example the collector of a bipolar transistor or the active region of a MOS transistor, a mask layer having an opening is produced on the surface of a substrate. The surface of the substrate is exposed within the opening. The cross-section of the opening parallel to the surface of the substrate at the surface of the substrate projects laterally beyond that cross-section at the surface of the mask layer. The sidewall of the opening proceeds essentially perpendicularly relative to the surface of the substrate in the region of the surface of the mask layer and has a step-shaped profile in cross-section perpendicularly relative to the surface of the substrate. The single-crystal region is formed by selective epitaxy within the opening.

Abstract translation: 为了在衬底上产生横向受限的单晶区域，例如双极晶体管的集电极或MOS晶体管的有源区，在衬底的表面上产生具有开口的掩模层。 衬底的表面暴露在开口内。 在衬底表面处平行于衬底表面的开口的横截面横向突出超过掩模层表面处的横截面。 开口的侧壁在掩模层的表面的区域中基本上相对于衬底的表面垂直地延伸，并且具有相对于衬底的表面垂直的横截面的阶梯形轮廓。 单晶区域通过开口内的选择性外延形成。

公开(公告)号：US4980742A

公开(公告)日：1990-12-25

申请号：US335362

申请日：1989-04-10

Applicant: Reinhard Stengl ,  Klaus G. Oppermann

Inventor： Reinhard Stengl ,  Klaus G. Oppermann

IPC: H01L29/744 ,  H01L29/06 ,  H01L29/10 ,  H01L29/36 ,  H01L29/74 ,  H01L29/749

CPC classification number: H01L29/0623 ,  H01L29/1016 ,  H01L29/36

Abstract: A turn-off thyristor whereby an n-base layer not contacted by a gate electrode has at least one thin semiconductor layer inserted into it that is oppositely doped. Its distance from a pn-junction between a p-base and the n-base is selected so small that the maximum field strength of the space charge zone building up at this pn-junction upon turn-off of the thyristor is limited to a non-critical value at which an avalanche breakdown with respect to the charge carriers to be cleared out does not yet occur.

Abstract translation: 一种截止晶闸管，其中不与栅电极接触的n基层具有插入其中的相对掺杂的至少一个薄半导体层。 其与p基极和n基极之间的pn结的距离被选择得很小，使得在晶闸管截止时在该pn结处积聚的空间电荷区域的最大场强被限制为非 - 相对于要清除的电荷载体的雪崩击穿的临界值尚未发生。

公开(公告)号：US20050233536A1

公开(公告)日：2005-10-20

申请号：US11153062

申请日：2005-06-15

Applicant: Josef Bock ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schafer

Inventor： Josef Bock ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schafer

IPC: H01L21/331 ,  H01L29/06 ,  H01L29/08 ,  H01L29/737

CPC classification number: H01L29/66287 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/167 ,  H01L29/66242 ,  H01L29/7371 ,  H01L29/7378

Abstract: The invention relates to a method for producing a bipolar transistor. A semiconductor substrate is provided that encompasses a collector area of a first conductivity type, which is embedded therein and is bare towards the top. A monocrystalline base area is provided and a base-connecting area of the second conductivity type is provided above the base area. An insulating area is provided above the base-connecting area and a window is formed in the insulating area and the base-connecting area so as to at least partly expose the base area. An insulating sidewall spacer is provided in the window in order to insulate the base-connecting area. An emitter layer which forms a monocrystalline emitter area above the base area and a polycrystalline emitter area above the insulating area and the sidewall spacer is differentially deposited and structured, and a tempering step is carried out.

Abstract translation: 本发明涉及一种制造双极晶体管的方法。 提供了一种半导体衬底，其包含嵌入其中并且朝向顶部裸露的第一导电类型的集电极区域。 提供单晶基底区域，并且在基底区域上方设置第二导电类型的基底连接区域。 绝缘区域设置在基底连接区域上方，并且在绝缘区域和基底连接区域中形成窗口，以便至少部分地暴露基部区域。 在窗口中设置绝缘侧壁间隔件，以便使基部连接区域绝缘。 在绝缘区域之上形成单晶发射极区域和绝缘区域上方的多晶发射极区域的发射极层被差异地沉积和结构化，并进行回火步骤。

公开(公告)号：US06887437B1

公开(公告)日：2005-05-03

申请号：US09718902

申请日：2000-11-22

Applicant: Volker Lehmann ,  Stefan Ottow ,  Reinhard Stengl ,  Hans Reisinger ,  Hermann Wendt

Inventor： Volker Lehmann ,  Stefan Ottow ,  Reinhard Stengl ,  Hans Reisinger ,  Hermann Wendt

IPC: B01D50/00 ,  B01D53/34 ,  B01J19/00 ,  C23C16/02 ,  C23C16/26

CPC classification number: C23C16/26 ,  B01J19/0093 ,  B01J2219/00788 ,  B01J2219/00822 ,  B01J2219/00824 ,  B01J2219/00828 ,  B01J2219/00835 ,  B01J2219/00844 ,  B01J2219/00862 ,  C23C16/0245

Abstract: A reactor configuration contains a housing connected to a silicon wafer. The silicon wafer has pores extending from a first main area of the silicon wafer into an interior of the silicon wafer, preferably as far as a second main area of the silicon wafer. A catalyst layer at least partly covers the surface of the pores.

Abstract translation: 反应器构造包含连接到硅晶片的壳体。 硅晶片具有从硅晶片的第一主区域延伸到硅晶片的内部的孔，优选地直到硅晶片的第二主区域。 催化剂层至少部分地覆盖孔的表面。

公开(公告)号：US06867105B2

公开(公告)日：2005-03-15

申请号：US10215152

申请日：2002-08-08

Applicant: Reinhard Stengl ,  Thomas Meister ,  Herbert Schäfer ,  Martin Franosch

Inventor： Reinhard Stengl ,  Thomas Meister ,  Herbert Schäfer ,  Martin Franosch

IPC: H01L21/331 ,  H01L29/732

CPC classification number: H01L29/66287 ,  H01L29/7322

Abstract: A bipolar transistor includes a first layer with a collector. A second layer has a base cutout for a base. A third layer includes a lead for the base. The third layer is formed with an emitter cutout for an emitter. An undercut is formed in the second layer adjoining the base cutout. The base is at least partially located in the undercut. In order to obtain a low transition resistance between the lead and the base, an intermediate layer is provided between the first and the second layer. The intermediate layer is selectively etchable with respect to the second layer. At least in the region of the undercut between the lead and the base, a base connection zone is provided that can be adjusted independent of other production conditions. The intermediate layer is removed in a contact region with the base.

Abstract translation: 双极晶体管包括具有集电极的第一层。 第二层具有用于基座的基部切口。 第三层包括用于底座的引线。 第三层形成有用于发射极的发射极切口。 在与基座切口相邻的第二层中形成底切。 基部至少部分位于底切中。 为了在引线和基底之间获得低的过渡电阻，在第一和第二层之间设置中间层。 中间层相对于第二层可选择性地蚀刻。 至少在引线和基座之间的底切区域中，提供可以独立于其他生产条件进行调节的基础连接区域。 在与基底的接触区域中去除中间层。

公开(公告)号：US06614575B1

公开(公告)日：2003-09-02

申请号：US09636521

申请日：2000-08-10

Applicant: Ulrike Grüning ,  Volker Lehmann ,  Reinhard Stengl ,  Hermann Wendt ,  Hans Reisinger

Inventor： Ulrike Grüning ,  Volker Lehmann ,  Reinhard Stengl ,  Hermann Wendt ,  Hans Reisinger

IPC: G02F103

CPC classification number: B82Y20/00 ,  G02B6/1225

Abstract: An optical structure includes a substrate having semiconductor material and a grating structure. The grating structure has the property of emitting at least one frequency band so that light having a frequency from that frequency band cannot propagate in the grating structure. The grating structure has a configuration of pores and a defective region. The pores are disposed outside the defective region in a periodic array, and the periodic array is disturbed in the defective region. A surface of the grating structure is provided with a conductive layer at least in the vicinity of the defective region. A method for producing the optical structure is also provided.

Abstract translation: 光学结构包括具有半导体材料和光栅结构的衬底。 光栅结构具有发射至少一个频带的特性，使得具有来自该频带的频率的光不能在光栅结构中传播。 光栅结构具有孔和缺陷区的构造。 孔以周期性阵列设置在缺陷区域的外侧，并且周期性阵列在缺陷区域中受到干扰。 光栅结构的表面至少在缺陷区域附近设置有导电层。 还提供了一种用于制造光学结构的方法。

公开(公告)号：US06614066B2

公开(公告)日：2003-09-02

申请号：US10113418

申请日：2002-04-01

Applicant: Reinhard Stengl ,  Hans Reisinger ,  Thomas Haneder ,  Harald Bachhofer

Inventor： Reinhard Stengl ,  Hans Reisinger ,  Thomas Haneder ,  Harald Bachhofer

IPC: H01L2976

CPC classification number: H01L29/516 ,  H01L29/78391

Abstract: A first source-drain region, a channel region, and a second source-drain region are arranged one after another in a semiconductor substrate. At least the surface of the channel region and parts of the first source-drain region are covered by a dielectric layer. A ferroelectric layer is disposed on the surface of the dielectric layer between two polarization electrodes. A gate electrode is arranged on the surface of the dielectric layer. The thickness of the dielectric layer is dimensioned such that a remanent polarization of the ferroelectric layer, which is aligned between the two polarization electrodes, produces compensation charges in part of the channel region. The ferroelectric transistor is suitable as a memory cell for a memory cell configuration.

公开(公告)号：US6117790A

公开(公告)日：2000-09-12

申请号：US302655

申请日：1999-04-30

Applicant: Herbert Schafer ,  Martin Franosch ,  Reinhard Stengl ,  Gerrit Lange ,  Hans Reisinger ,  Hermann Wendt ,  Volker Lehmann

Inventor： Herbert Schafer ,  Martin Franosch ,  Reinhard Stengl ,  Gerrit Lange ,  Hans Reisinger ,  Hermann Wendt ,  Volker Lehmann

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/00

CPC classification number: H01L27/10852 ,  H01L27/10817 ,  H01L28/82

Abstract: A method for fabricating a capacitor for a semiconductor memory configuration. In this case, a selectively etchable material is applied to a conductive support, which is connected to a semiconductor body via a contact hole in an insulator layer, and patterned. A first conductive layer is applied thereon and patterned. A hole is introduced into the first conductive layer, through which hole the selectively etchable material is etched out. A cavity is produced under the first conductive layer in the process. The inner surface of the cavity and the outer surface of the first conductive layer are provided with a dielectric layer, to which a second conductive layer is applied and patterned.

Abstract translation: 一种制造用于半导体存储器配置的电容器的方法。 在这种情况下，将可选择的可蚀刻材料施加到导电支撑件，该导电支撑件通过绝缘体层中的接触孔连接到半导体本体并且被图案化。 在其上施加第一导电层并图案化。 在第一导电层中引入一个孔，通过该孔蚀刻可选择性蚀刻的材料。 在该过程中在第一导电层下方产生空腔。 空腔的内表面和第一导电层的外表面设置有电介质层，第二导电层被施加并图案化。

公开(公告)号：US6018174A

公开(公告)日：2000-01-25

申请号：US105580

申请日：1998-06-26

Applicant: Martin Schrems ,  Jack Mandelman ,  Joachim Hoepfner ,  Herbert Schaefer ,  Reinhard Stengl

Inventor： Martin Schrems ,  Jack Mandelman ,  Joachim Hoepfner ,  Herbert Schaefer ,  Reinhard Stengl

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94 ,  H01L29/76

CPC classification number: H01L27/10861 ,  H01L29/945

Abstract: A bottle-shaped trench capacitor having an expanded lower trench portion with an epi layer therein. The epi layer serves as the buried plate of the trench capacitor. A diffusion region surrounds the expanded lower trench portion to enhance the dopant concentration of the epi layer. The diffusion region is formed by, for example, gas phase doping, plasma doping, or plasma immersion ion implantation.

Abstract translation: 一种瓶形沟槽电容器，其具有扩展的下沟槽部分，其中具有外延层。 外延层用作沟槽电容器的掩埋板。 扩散区域围绕扩展的下沟槽部分以增强外延层的掺杂剂浓度。 扩散区域通过例如气相掺杂，等离子体掺杂或等离子体浸入离子注入形成。

公开(公告)号：US5994746A

公开(公告)日：1999-11-30

申请号：US232083

申请日：1999-01-15

Applicant: Hans Reisinger ,  Reinhard Stengl ,  Franz Hofmann ,  Wolfgang Krautschneider ,  Josef Willer

Inventor： Hans Reisinger ,  Reinhard Stengl ,  Franz Hofmann ,  Wolfgang Krautschneider ,  Josef Willer

IPC: G11C17/08 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/112 ,  H01L27/115

CPC classification number: H01L27/11273 ,  H01L27/112

Abstract: The memory cell has transistors that are arranged three-dimensionally. Vertical MOS transistors are arranged on the sidewalls of semiconductor webs, and a plurality of transistors are arranged one above the other on each sidewall. The transistors that are arranged one above the other on a sidewall are connected in series.

Abstract translation: 存储单元具有三维布置的晶体管。 垂直MOS晶体管布置在半导体薄片的侧壁上，并且多个晶体管彼此并排设置在每个侧壁上。 在侧壁上一个上下配置的晶体管串联连接。