公开(公告)号：US07053165B2

公开(公告)日：2006-05-30

申请号：US10600104

申请日：2003-06-20

申请人： Masayuki Furumiya ,  Ryota Yamamoto

发明人： Masayuki Furumiya ,  Ryota Yamamoto

IPC分类号： H01L29/00

CPC分类号： H01L28/10 ,  H01F17/0006 ,  H01F27/34 ,  H01F41/046 ,  H01L23/5227 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit device, and method of manufacturing the same, includes an inductor with improved inductance and an improved quality factor (Q-factor) that can be miniaturized. In one example, an inductor (3) is provided on an insulating layer (2) of a multilayer interconnection layer (1). The inductor (3) is formed by a spiral arrangement of a wiring (3a). A lamination film (14) is provided in an internal region (13) of an inductor (3) on insulating layer (2), and can be formed by laminating a titanium-tungsten (TiW) layer (9), a copper (Cu) layer (10), a ferromagnetic substance layer (15) made of nickel (Ni), a Cu layer (11), and a TiW layer (12), in that order. A lower surface of ferromagnetic substance layer (15) can be lower than an upper surface of wiring layer (3a), and an upper surface of ferromagnetic substance layer (15) can be higher than a lower surface of wiring layer (3a). As a result, a lower portion of ferromagnetic substance layer (15) can be at the same layer (level) as wiring layer (3a). An upper surface of lamination film (14) can be made higher than a wiring layer (3a), and a lower surface of lamination film (14) can be made lower than a lower surface of a wiring layer (3a).

摘要翻译： 半导体集成电路器件及其制造方法包括具有改善的电感的电感器和可以小型化的改进的品质因数（Q因子）。 在一个示例中，电感器（3）设置在多层互连层（1）的绝缘层（2）上。 电感器（3）由布线（3a）的螺旋布置形成。 层叠膜（14）设置在绝缘层（2）上的电感器（3）的内部区域（13）中，并且可以通过层压钛 - 钨（TiW）层（9），铜（Cu ）层（10），由镍（Ni）制成的铁磁物质层（15），Cu层（11）和TiW层（12）。 铁磁物质层（15）的下表面可以比布线层（3a）的上表面低，并且铁磁物质层（15）的上表面可以高于布线层（3a）的下表面， 。 结果，铁磁物质层（15）的下部可以与布线层（3a）处于相同的层（层）。 层叠膜（14）的上表面可以比布线层（3a）高，并且层压膜（14）的下表面可以被制成低于布线层（3a）的下表面。

公开(公告)号：US20060087004A1

公开(公告)日：2006-04-27

申请号：US11247296

申请日：2005-10-12

申请人： Masayuki Furumiya ,  Kuniko Kikuta ,  Ryota Yamamoto ,  Makoto Nakayama

发明人： Masayuki Furumiya ,  Kuniko Kikuta ,  Ryota Yamamoto ,  Makoto Nakayama

IPC分类号： H01L29/00

CPC分类号： H01L23/5223 ,  H01L27/0805 ,  H01L28/87 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device has a semiconductor substrate, a multi-layered wiring construction formed over the semiconductor device, and a metal-insulator-metal (MIM) capacitor arrangement established in the multi-layered wiring construction. The MIM capacitor arrangement includes first, second, third, fourth, fifth, and sixth electrode structures, which are arranged in order in parallel with each other at regular intervals. The first, second, fifth and sixth electrode structures are electrically connected to each other so as to define a first capacitor, and the third and fourth electrode structures are electrically connected to each other so as to define a second capacitor.

公开(公告)号：US20050189602A1

公开(公告)日：2005-09-01

申请号：US11066534

申请日：2005-02-28

申请人： Ryota Yamamoto ,  Yasutaka Nakashiba

发明人： Ryota Yamamoto ,  Yasutaka Nakashiba

IPC分类号： H01L21/76 ,  H01L21/761 ,  H01L21/765 ,  H01L21/822 ,  H01L23/58 ,  H01L27/04 ,  H01L29/00 ,  H01L29/06 ,  H01L29/51 ,  H01L29/74 ,  H01L31/111

CPC分类号： H01L21/765 ,  H01L21/761 ,  H01L29/0619 ,  H01L2924/0002 ,  H01L2924/00

摘要： An insulating film is provided in a region surrounding a circuit region on a p type silicon substrate, and a frame-shaped electrode is provided to surround the circuit region on the insulating film. The region directly under the electrode at the surface of the p type silicon substrate is formed as a non-doped region with no impurity implanted. Then, a positive power supply potential is applied to the electrode. In this way, a depletion layer is formed directly under the electrode at the surface of the p type silicon substrate. Consequently, the substrate noise is shielded.

摘要翻译： 在p型硅衬底上的电路区域周围的区域中设置绝缘膜，并且设置框状电极以围绕绝缘膜上的电路区域。 在p型硅衬底的表面的正下方的区域形成为没有杂质注入的非掺杂区域。 然后，向电极施加正电源电位。 以这种方式，在p型硅衬底的表面下方的电极正下方形成耗尽层。 因此，衬底噪声被屏蔽。

公开(公告)号：US08378454B2

公开(公告)日：2013-02-19

申请号：US13173709

申请日：2011-06-30

申请人： Masayuki Furumiya ,  Kuniko Kikuta ,  Ryota Yamamoto ,  Makoto Nakayama

发明人： Masayuki Furumiya ,  Kuniko Kikuta ,  Ryota Yamamoto ,  Makoto Nakayama

IPC分类号： H01L21/02

CPC分类号： H01L23/5223 ,  H01L27/0805 ,  H01L28/87 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device has a semiconductor substrate, a multi-layered wiring construction formed over the semiconductor device, and a metal-insulator-metal (MIM) capacitor arrangement established in the multi-layered wiring construction. The MIM capacitor arrangement includes first, second, third, fourth, fifth, and sixth electrode structures, which are arranged in order in parallel with each other at regular intervals. The first, second, fifth and sixth electrode structures are electrically connected to each other so as to define a first capacitor, and the third and fourth electrode structures are electrically connected to each other so as to define a second capacitor.

摘要翻译： 半导体器件具有形成在半导体器件上的半导体衬底，多层布线结构以及在多层布线结构中建立的金属 - 绝缘体 - 金属（MIM）电容器布置。 MIM电容器装置包括以规则的间隔彼此平行地排列的第一，第二，第三，第四，第五和第六电极结构。 第一，第二，第五和第六电极结构彼此电连接以限定第一电容器，并且第三和第四电极结构彼此电连接以限定第二电容器。

公开(公告)号：US07432170B2

公开(公告)日：2008-10-07

申请号：US11017695

申请日：2004-12-22

申请人： Hiroaki Ohkubo ,  Ryota Yamamoto ,  Masayuki Furumiya ,  Masaharu Sato ,  Kuniko Kikuta ,  Makoto Nakayama ,  Yasutaka Nakashiba

发明人： Hiroaki Ohkubo ,  Ryota Yamamoto ,  Masayuki Furumiya ,  Masaharu Sato ,  Kuniko Kikuta ,  Makoto Nakayama ,  Yasutaka Nakashiba

IPC分类号： H01L21/20

CPC分类号： H01L28/40 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： On a silicon substrate, a first insulation layer, a lower conductive layer, a capacitor-insulator layer, and an upper conductive layer are formed in that order. Then, a first resist pattern is formed, the upper conductive layer is etched to form an upper electrode, and the capacitor-insulator layer is successively etched partway under the same etching condition as that of the upper conductive layer. Next, second resist pattern is formed, the remaining part of the capacitor-insulator layer is etched to form a second insulation layer, and the lower conductive layer is successively etched under the same etching condition as that of the capacitor-insulator layer so as to form a lower electrode and a lower wiring. In this manner, an MiM capacitor element constituted by the upper electrode, a part of the second insulation layer, and the lower electrode can be fabricated.

摘要翻译： 在硅衬底上依次形成第一绝缘层，下导电层，电容器 - 绝缘体层和上导电层。 然后，形成第一抗蚀剂图案，蚀刻上导电层以形成上电极，并且在与上导电层的蚀刻条件相同的蚀刻条件下，电容器 - 绝缘体层被连续蚀刻。 接下来，形成第二抗蚀剂图案，蚀刻电容器 - 绝缘体层的其余部分以形成第二绝缘层，并且在与电容器 - 绝缘体层的蚀刻条件相同的蚀刻条件下，依次蚀刻下导电层，以便 形成下电极和下布线。 以这种方式，可以制造由上电极，第二绝缘层的一部分和下电极构成的MiM电容器元件。

公开(公告)号：US07361845B2

公开(公告)日：2008-04-22

申请号：US10352301

申请日：2003-01-27

申请人： Ryota Yamamoto ,  Masayuki Furumiya

发明人： Ryota Yamamoto ,  Masayuki Furumiya

IPC分类号： H05K3/02 ,  H05K3/10 ,  H05K1/16

CPC分类号： H01L23/5227 ,  H01L2924/0002 ,  Y10T29/49155 ,  H01L2924/00

摘要： Wiring lines for use at a high frequency having reduced resistance and/or inductance are disclosed that may be readily manufactured in a semiconductor integrated circuit. Wiring lines can include extension lines (2), connected to both ends of an inductor (1), that may each include divided wiring lines (2a and 2b) that are separated by a slit (3). A length, width and thickness of divided wiring lines (2a and 2b) can be essentially equal, resulting in divided wiring lines (2a and 2b) of essentially equal longitudinal resistance. A width of a slit (3) may preferably be greater than a width of each of divided wiring lines (2a and 2b).

摘要翻译： 公开了可以容易地在半导体集成电路中制造的具有降低的电阻和/或电感的高频使用的布线。 连接线可以包括连接到电感器（2）的两端的延伸线（2），每条线可以包括被狭缝（3）分开的划分的布线（2a和2b）。 分开的布线（2a和2b）的长度，宽度和厚度可以基本上相等，导致基本相等的纵向电阻的分开的布线（2a和2b）。 狭缝（3）的宽度优选地可以大于分开的布线（2a和2b）的宽度。

公开(公告)号：US20080048294A1

公开(公告)日：2008-02-28

申请号：US11892362

申请日：2007-08-22

申请人： Ryota Yamamoto

发明人： Ryota Yamamoto

IPC分类号： H01L29/00 ,  H05K9/00

CPC分类号： H01L23/585 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate; a circuit; a guard ring; a power source line; and a contact. The semiconductor substrate has a first conductive type. The circuit is formed on the semiconductor substrate. The guard ring is formed on the semiconductor substrate such that the guard ring surrounds the circuit. The power source line supplies an electric power both the circuit and the guard ring. The contact is formed on the guard ring and connects the guard ring and the power source line. The guard ring is composed of a semiconductor having a second conductive type opposite to the first conductive type. The contact is placed in an opposite side of a noise source over the circuit.

摘要翻译： 半导体器件包括半导体衬底; 电路 守卫环 电源线; 和联系人。 半导体衬底具有第一导电类型。 电路形成在半导体衬底上。 保护环形成在半导体基板上，使得保护环围绕电路。 电源线为电路和保护环提供电力。 触点形成在保护环上，并连接保护环和电源线。 保护环由具有与第一导电类型相反的第二导电类型的半导体构成。 触点放置在电路上的噪声源的相对侧。

公开(公告)号：US07091576B2

公开(公告)日：2006-08-15

申请号：US10460306

申请日：2003-06-13

申请人： Ryota Yamamoto ,  Masayuki Furumiya ,  Hiroaki Ohkubo ,  Yasutaka Nakashiba

发明人： Ryota Yamamoto ,  Masayuki Furumiya ,  Hiroaki Ohkubo ,  Yasutaka Nakashiba

IPC分类号： H01L29/00

CPC分类号： H01L28/10 ,  H01L21/76838 ,  H01L23/5227 ,  H01L23/53228 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed are an inductor for a semiconductor integrated circuit, which provides a wider cross-sectional area, significantly reduces the resistance to improve the Q value and has a highly uniform film thickness, and a method of fabricating the inductor. A spiral inductor is formed on a topmost interconnection layer of a multilayer interconnection layer formed by a damascene method. This inductor is formed by patterning a barrier metal layer on an insulation film, on which a topmost interconnection is formed, in such a way that the barrier metal layer contacts the topmost interconnection, then forming a protective insulation film on an entire surface of the barrier metal layer, forming an opening in that portion of the protective insulation film which lies over the barrier metal layer, forming a thick Cu film with the barrier metal layer serving as a plating electrode, and performing wet etching of the Cu film. This process can allow the inductor to be so formed as to be thick and have a wide line width.

公开(公告)号：US20100148307A1

公开(公告)日：2010-06-17

申请号：US12707121

申请日：2010-02-17

申请人： Masayuki FURUMIYA ,  Kuniko KIKUTA ,  Ryota YAMAMOTO ,  Makoto NAKAYAMA

发明人： Masayuki FURUMIYA ,  Kuniko KIKUTA ,  Ryota YAMAMOTO ,  Makoto NAKAYAMA

IPC分类号： H01L29/92

CPC分类号： H01L23/5223 ,  H01L27/0805 ,  H01L28/87 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device has a semiconductor substrate, a multi-layered wiring construction formed over the semiconductor device, and a metal-insulator-metal (MIM) capacitor arrangement established in the multi-layered wiring construction. The MIM capacitor arrangement includes first, second, third, fourth, fifth, and sixth electrode structures, which are arranged in order in parallel with each other at regular intervals. The first, second, fifth and sixth electrode structures are electrically connected to each other so as to define a first capacitor, and the third and fourth electrode structures are electrically connected to each other so as to define a second capacitor.

摘要翻译： 半导体器件具有形成在半导体器件上的半导体衬底，多层布线结构以及在多层布线结构中建立的金属 - 绝缘体 - 金属（MIM）电容器布置。 MIM电容器装置包括以规则的间隔彼此平行地排列的第一，第二，第三，第四，第五和第六电极结构。 第一，第二，第五和第六电极结构彼此电连接以限定第一电容器，并且第三和第四电极结构彼此电连接以限定第二电容器。

公开(公告)号：US07705422B2

公开(公告)日：2010-04-27

申请号：US11247296

申请日：2005-10-12

申请人： Masayuki Furumiya ,  Kuniko Kikuta ,  Ryota Yamamoto ,  Makoto Nakayama

发明人： Masayuki Furumiya ,  Kuniko Kikuta ,  Ryota Yamamoto ,  Makoto Nakayama

IPC分类号： H01L29/00

CPC分类号： H01L23/5223 ,  H01L27/0805 ,  H01L28/87 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device has a semiconductor substrate, a multi-layered wiring construction formed over the semiconductor device, and a metal-insulator-metal (MIM) capacitor arrangement established in the multi-layered wiring construction. The MIM capacitor arrangement includes first, second, third, fourth, fifth, and sixth electrode structures, which are arranged in order in parallel with each other at regular intervals. The first, second, fifth and sixth electrode structures are electrically connected to each other so as to define a first capacitor, and the third and fourth electrode structures are electrically connected to each other so as to define a second capacitor.

摘要翻译： 半导体器件具有形成在半导体器件上的半导体衬底，多层布线结构以及在多层布线结构中建立的金属 - 绝缘体 - 金属（MIM）电容器布置。 MIM电容器装置包括以规则的间隔彼此平行地排列的第一，第二，第三，第四，第五和第六电极结构。 第一，第二，第五和第六电极结构彼此电连接以限定第一电容器，并且第三和第四电极结构彼此电连接以限定第二电容器。