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    Selectable clock input
    24.
    发明授权
    Selectable clock input 失效
    可选择的时钟输入

    公开(公告)号：US06990041B2

    公开(公告)日：2006-01-24

    申请号：US10747225

    申请日：2003-12-30

    Applicant: Christopher S. Johnson ,  Scott Schaefer

    Inventor： Christopher S. Johnson ,  Scott Schaefer

    IPC: G11C8/00

    CPC classification number: G11C7/225 ,  G11C7/1045 ,  G11C7/22 ,  G11C8/18 ,  G11C2207/2227

    Abstract: A memory device having a mode register with a selectable bit which sets the memory device to operate with a selected one of a plurality of possible clock input signals, for example, a single clock input or differential clock input.

    Abstract translation: 一种具有模式寄存器的存储器件，其具有可选择位，该可选位将存储器件设置为使用多个可能的时钟输入信号（例如，单个时钟输入或差分时钟输入）中选定的一个进行操作。

    Memory modules having accurate operating current values stored thereon and methods for fabricating and implementing such devices
    26.
    发明申请
    Memory modules having accurate operating current values stored thereon and methods for fabricating and implementing such devices 有权
    具有存储在其上的精确工作电流值的存储器模块以及用于制造和实施这种装置的方法

    公开(公告)号：US20050223206A1

    公开(公告)日：2005-10-06

    申请号：US10816239

    申请日：2004-04-01

    Applicant: Jeffery Janzen ,  Scott Schaefer ,  Todd Farrell

    Inventor： Jeffery Janzen ,  Scott Schaefer ,  Todd Farrell

    IPC: G06F15/177

    CPC classification number: G06F11/3037 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/3058

    Abstract: Memory modules having accurate operating current values stored thereon and methods for fabricating and implementing such devices to improve system performance. Memory modules comprising a number of volatile memory devices may be fabricated. Operating current values for specific memory devices on the memory module or a specific lot in which the memory devices are fabricated may be stored on a non-volatile memory device on the memory module. A system may be configured in accordance with the operating current values stored on the non-volatile memory device such that operating current thresholds are not exceeded.

    Abstract translation: 具有存储在其上的精确工作电流值的存储器模块以及用于制造和实施这些装置以改善系统性能的方法。 可以制造包括多个易失性存储器件的存储器模块。 存储器模块或存储器件制造的特定批次中的特定存储器件的工作电流值可存储在存储器模块上的非易失性存储器件上。 可以根据存储在非易失性存储器件上的工作电流值来配置系统，使得不超过工作电流阈值。

    Method of reducing standby current during power down mode
    27.
    发明授权
    Method of reducing standby current during power down mode 失效
    降低待机电流的方法

    公开(公告)号：US06836437B2

    公开(公告)日：2004-12-28

    申请号：US10649627

    申请日：2003-08-28

    Applicant: Wen Li ,  Mark R. Thomann ,  Daniel R. Loughmiller ,  Scott Schaefer

    Inventor： Wen Li ,  Mark R. Thomann ,  Daniel R. Loughmiller ,  Scott Schaefer

    IPC: G11C700

    CPC classification number: G11C5/14

    Abstract: An apparatus and method for reducing the power consumption of a memory integrated circuit during a period of power down mode operation by interrupting the clocking transitions of a delay line. A memory integrated circuit may include a delay lock loop including a plurality of delay elements connected to one another in series and adapted to delay propagation of the signal of a free running clock. When the delayed signal is not required, as during a period of power down mode operation, the free running clock signal is prevented from reaching the delay lock loop. Consequently the delay elements do not toggle, and power associated with delay element toggling is saved.

    Method for initializing and reprogramming a control operation feature of a memory device
    28.
    发明授权
    Method for initializing and reprogramming a control operation feature of a memory device 失效
    用于初始化和重新编程存储器件的控制操作特征的方法

    公开(公告)号：US06175901B1

    公开(公告)日：2001-01-16

    申请号：US08719811

    申请日：1996-09-25

    Applicant: Brett Williams ,  Scott Schaefer

    Inventor： Brett Williams ,  Scott Schaefer

    IPC: G06F1200

    CPC classification number: G11C11/4096 ,  G11C7/1045 ,  G11C7/1072 ,  G11C11/4072

    Abstract: A method for programming a synchronous dynamic random access memory (SDRAM) device including a memory array is disclosed. In the method, the SDRAM device is initially programmed to have a first control operating option in response to a first command. Reprogramming of the SDRAM device includes a second control operating option in response to a second command. The array remains simultaneously active in response to an active internal row address signal while the control operation feature is programmed to have the second control operating option.

    Abstract translation: 公开了一种用于编程包括存储器阵列的同步动态随机存取存储器（SDRAM）装置的方法。 在该方法中，SDRAM装置最初被编程为具有响应于第一命令的第一控制操作选项。 SDRAM设备的重新编程包括响应于第二命令的第二控制操作选项。 当控制操作功能被编程为具有第二控制操作选项时，该阵列响应于活动的内部行地址信号而保持同时有效。

    Synchronous DRAM memory with asynchronous column decode
    29.
    发明授权
    Synchronous DRAM memory with asynchronous column decode 有权
    具有异步列解码的同步DRAM存储器

    公开(公告)号：US6111814A

    公开(公告)日：2000-08-29

    申请号：US315649

    申请日：1999-05-20

    Applicant: Scott Schaefer

    Inventor： Scott Schaefer

    IPC: G11C7/10 ,  G11C8/00 ,  G11C8/06 ,  G11C11/408

    CPC classification number: G11C7/22 ,  G11C11/4076 ,  G11C11/4082 ,  G11C11/4087 ,  G11C7/1018 ,  G11C7/1027 ,  G11C7/1072 ,  G11C8/06 ,  G11C8/10 ,  G11C8/18

    Abstract: Disclosed is a synchronous DRAM memory module with control circuitry that allows the memory module to operate partially asynchronously. Specifically, a circuit is disclosed which utilizes address transition detection to begin decoding the column-address immediately after a new column-address is present on the address bus lines and without waiting for the column-address strobe signal to synchronize with the rising or falling edge of the synchronizing clock signal. Also disclosed is a manner of controlling the latching circuitry whereby each new column-address may be decoded and held within a buffer until the column-address strobe signal notifies the circuitry that the column-address is correct and is to be input into the microprocessor. Thus, each new column-address will be decoded immediately after it is present on the address lines and undesired column-addresses will be discarded, while desired column-addresses are input into the memory array bank immediately upon the presence of the column-address strobe which denotes that the column-address is final. The present invention improves the access times of read and write operations in synchronous DRAM memory by up to a complete clock cycle.

    Abstract translation: 公开了具有控制电路的同步DRAM存储器模块，其允许存储器模块部分地异步操作。 具体地，公开了一种电路，其利用地址转换检测在地址总线上存在新的列地址之后立即开始对列地址进行解码，而不等待列地址选通信号与上升沿或下降沿同步 的同步时钟信号。 还公开了一种控制锁存电路的方式，由此每个新的列地址可以被解码并保持在缓冲器中，直到列地址选通信号通知电路列地址是正确的并且要被输入微处理器。 因此，每个新的列地址在它存在于地址线上之后将立即被解码，并且不期望的列地址将被丢弃，而在列地址选通存在时，期望的列地址被立即输入到存储器阵列组中 这表示列地址是final。 本发明提高了同步DRAM存储器中的读写操作的访问时间，直到完整的时钟周期。

    Initializing and reprogramming circuitry for state independent memory array burst operations control
    30.
    发明授权
    Initializing and reprogramming circuitry for state independent memory array burst operations control 失效
    初始化和重新编程电路，用于状态独立存储器阵列脉冲串操作控制

    公开(公告)号：US5896551A

    公开(公告)日：1999-04-20

    申请号：US228051

    申请日：1994-04-15

    Applicant: Brett Williams ,  Scott Schaefer

    Inventor： Brett Williams ,  Scott Schaefer

    IPC: G11C5/06 ,  G11C7/10 ,  G11C11/4072 ,  G11C11/4096 ,  G06F13/28

    CPC classification number: G11C5/066 ,  G11C11/4072 ,  G11C11/4096 ,  G11C7/1042 ,  G11C7/1045 ,  G11C7/1072

    Abstract: A synchronous dynamic random access memory (SDRAM) device having a master control circuit for accepting a first command and a second command and having an initialization and reprogramming circuit. The master control circuit generates and initialization signal in response to the first command and generates a reprogramming signal in response to the second command. The initialization and reprogramming circuit responds to the initialization signal to control initial programming of a burst control operation feature and responds to the reprogramming signal to control a reprogramming of the burst control operation feature.

    Abstract translation: 一种具有用于接收第一命令和第二命令并具有初始化和重新编程电路的主控制电路的同步动态随机存取存储器（SDRAM）装置。 主控制电路响应于第一命令产生和初始化信号，并且响应于第二命令产生重编程信号。 初始化和重新编程电路响应于初始化信号以控制突发控制操作特征的初始编程，并响应重编程信号以控制突发控制操作特征的重新编程。

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