公开(公告)号：US07833846B1

公开(公告)日：2010-11-16

申请号：US12591360

申请日：2009-11-17

申请人： Hee-Dong Choi ,  Seong-Moh Seo

发明人： Hee-Dong Choi ,  Seong-Moh Seo

IPC分类号： H01L21/00 ,  H01L29/04 ,  H01L21/336 ,  H01L29/786

CPC分类号： H01L27/124 ,  H01L27/1288 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66765

摘要： A method of fabricating an array substrate includes forming a buffer layer; forming a gate electrode on the buffer layer, a gate insulating layer on the gate electrode and an active layer on the gate insulating layer, the gate electrode including a bottom pattern, a middle pattern and a top pattern; forming an interlayer insulating layer, the first and second contact holes respectively exposing both sides of the active layer; forming first and second barrier patterns, first and second ohmic contact patterns, a source electrode, a drain, and a data line; forming a first passivation layer including a gate contact hole exposing the gate electrode; forming a gate line on the first passivation layer and contacting the gate electrode through the gate contact hole; forming a second passivation layer on the gate line; and forming a pixel electrode on the second passivation layer and contacting the drain electrode.

摘要翻译： 制造阵列基板的方法包括形成缓冲层; 在所述缓冲层上形成栅电极，在所述栅电极上形成栅极绝缘层，在所述栅极绝缘层上形成有源层，所述栅电极包括底部图案，中间图案和顶部图案; 形成层间绝缘层，所述第一和第二接触孔分别暴露所述有源层的两侧; 形成第一和第二屏障图案，第一和第二欧姆接触图案，源电极，漏极和数据线; 形成包括暴露栅电极的栅极接触孔的第一钝化层; 在所述第一钝化层上形成栅极线，并通过所述栅极接触孔与所述栅电极接触; 在栅极线上形成第二钝化层; 以及在所述第二钝化层上形成像素电极并与所述漏电极接触。

公开(公告)号：US06833666B2

公开(公告)日：2004-12-21

申请号：US10095111

申请日：2002-03-12

申请人： Seong-Moh Seo ,  Jae-Bon Koo

发明人： Seong-Moh Seo ,  Jae-Bon Koo

IPC分类号： H01J162

CPC分类号： H01L29/66757 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1288 ,  H01L27/3244 ,  H01L27/3265

摘要： A flat panel display device having a high capacitance and a high aperture ratio. A thin film transistor and a capacitor are formed on an insulating substrate. The thin film transistor includes a semiconductor layer, a gate electrode and source and drain electrodes. The capacitor has first and second capacitor electrodes and a dielectric layer. An insulating layer is formed over the transistor to insulate the gate electrode from the source and drain electrodes, and a portion of the insulating layer is formed as the dielectric layer between the first and second capacitor electrodes. A non-planar shape of the first capacitor electrode and a conforming shape of the dielectric layer and a second capacitor electrode increase a capacitance of the capacitor. The portion of the insulating layer serving as the capacitor dielectric is formed to be thinner than the portion of the insulating layer formed over the gate electrode.

摘要翻译： 具有高电容和高开口率的平板显示装置。 在绝缘基板上形成薄膜晶体管和电容器。 薄膜晶体管包括半导体层，栅极电极和源极和漏极。 电容器具有第一和第二电容器电极和电介质层。 在晶体管上形成绝缘层以使栅电极与源电极和漏电极绝缘，并且绝缘层的一部分形成为第一和第二电容器电极之间的电介质层。 第一电容器电极的非平面形状和电介质层和第二电容器电极的适形形状增加了电容器的电容。 用作电容器电介质的绝缘层的部分形成为比形成在栅电极上的绝缘层的部分更薄。

公开(公告)号：US06822717B2

公开(公告)日：2004-11-23

申请号：US10705898

申请日：2003-11-13

申请人： Seong Moh Seo ,  Hyun Ho Shin ,  Young Jin Oh ,  Hyun Chang Lee ,  Chang Yeon Kim

发明人： Seong Moh Seo ,  Hyun Ho Shin ,  Young Jin Oh ,  Hyun Chang Lee ,  Chang Yeon Kim

IPC分类号： G02F11343

CPC分类号： G02F1/136213 ,  G02F1/134363

摘要： An in-plane switching mode liquid crystal display device comprises first and second substrates, a plurality of gate and data bus lines defining pixel regions and arranged on the first substrate, a plurality of data electrodes on same plane of the data bus lines these some parts are overlapped with adjacent gate bus line, a passivation layer on the data electrodes, a plurality of common electrodes on the passivation layer these some parts are overlapped with adjacent data electrodes, and a liquid crystal layer between the first and second substrates.

摘要翻译： 面内切换模式液晶显示装置包括第一和第二基板，多个限定像素区域的栅极和数据总线线路，并布置在第一基板上，多个数据电极在数据总线的同一平面上，这些部分 与相邻栅极总线重叠，数据电极上的钝化层，钝化层上的多个公共电极，这些一些部分与相邻的数据电极重叠，以及在第一和第二基板之间的液晶层。

公开(公告)号：US06297866B1

公开(公告)日：2001-10-02

申请号：US09149746

申请日：1998-09-08

申请人： Seong Moh Seo ,  Yong Sung Ham ,  Jong Jin Park ,  Hyun Ho Shin ,  Young Soo Ahn

发明人： Seong Moh Seo ,  Yong Sung Ham ,  Jong Jin Park ,  Hyun Ho Shin ,  Young Soo Ahn

IPC分类号： G01K11349

CPC分类号： G02F1/134363

摘要： An in-plane switching mode liquid crystal display device includes first and second opposed substrates having inner surfaces in which a liquid crystal layer formed therebetween, a data bus line and a gate bus line arranged perpendicularly and/or horizontally in a matrix on the first substrate thereby defining a unit pixel region, and a pair of data electrode and common electrode applying a plane electric field in the liquid crystal layer, the electrodes being inclined with respect to the data bus line and parallel to each other.

摘要翻译： 面内切换模式液晶显示装置包括：第一和第二相对基板，其具有在其间形成的液晶层的内表面，在第一基板上以矩阵方式垂直和/或水平布置的数据总线和栅极总线 从而限定单位像素区域，以及在液晶层中施加平面电场的一对数据电极和公共电极，电极相对于数据总线倾斜并且彼此平行。

公开(公告)号：US5913113A

公开(公告)日：1999-06-15

申请号：US805386

申请日：1997-02-24

申请人： Seong Moh Seo

发明人： Seong Moh Seo

IPC分类号： H01L21/225 ,  H01L21/336 ,  H01L21/00 ,  H01L21/84

CPC分类号： H01L29/66757 ,  H01L29/66765 ,  H01L21/2255 ,  Y10S438/975

摘要： A method for fabricating a thin film transistor of a liquid crystal display device comprising the steps of introducing a dopant into an indium tin oxide layer or gate insulating layer with an ion shower doping process, forming an amorphous silicon layer thereon, exposing the amorphous silicon layer with a laser beam to diffuse the dopant into the amorphous layer and activate the dopant. As a result of the laser annealing, an n or p-type ohmic polysilicon layer and an intrinsic polysilicon channel layer can be formed. A gate electrode can also be formed on a gate insulating layer using a gate mask.

摘要翻译： 一种用于制造液晶显示装置的薄膜晶体管的方法，包括以下步骤：通过离子喷淋掺杂工艺将掺杂剂引入铟锡氧化物层或栅极绝缘层，在其上形成非晶硅层，暴露非晶硅层 用激光束将掺杂剂扩散到非晶层中并激活掺杂剂。 作为激光退火的结果，可以形成n型或p型欧姆多晶硅层和本征多晶硅沟道层。 也可以使用栅极掩模在栅极绝缘层上形成栅电极。

公开(公告)号：US08021937B2

公开(公告)日：2011-09-20

申请号：US12486453

申请日：2009-06-17

申请人： Hyung-Gu Roh ,  Byung-Chul Ahn ,  Hee-Dong Choi ,  Seong-Moh Seo ,  Jun-Min Lee

发明人： Hyung-Gu Roh ,  Byung-Chul Ahn ,  Hee-Dong Choi ,  Seong-Moh Seo ,  Jun-Min Lee

IPC分类号： H01L21/336

CPC分类号： H01L27/1285 ,  H01L21/268 ,  H01L27/1288

摘要： A method of fabricating an array substrate includes: forming a gate line and a gate electrode connected to the gate line; forming a gate insulating layer on the gate line and the gate insulting layer; sequentially forming an intrinsic amorphous silicon pattern and an impurity-doped amorphous silicon pattern on the gate insulating layer over the gate electrode; forming a data line on the gate insulating layer and source and drain electrodes on the impurity-doped amorphous silicon pattern, the data line crossing the gate line to define a pixel region, and the source and drain electrodes spaced apart from each other; removing a portion of the impurity-doped amorphous silicon pattern exposed through the source and drain electrodes to define an ohmic contact layer; irradiating a first laser beam onto the intrinsic amorphous silicon pattern through the source and drain electrode to form an active layer including a first portion of polycrystalline silicon and a second portion of amorphous silicon at both sides of the first portion; forming a passivation layer on the data line, the source electrode and the drain electrode, the passivation layer having a drain contact hole exposing the drain electrode; and forming a pixel electrode on the passivation layer in the pixel region, the pixel electrode connected to the drain electrode through the drain contact hole.

摘要翻译： 制造阵列基板的方法包括：形成栅极线和连接到栅极线的栅电极; 在栅极线和栅极绝缘层上形成栅极绝缘层; 在栅电极上的栅极绝缘层上依次形成本征非晶硅图案和杂质掺杂非晶硅图案; 在栅极绝缘层上形成数据线，在掺杂杂质的非晶硅图案上的源电极和漏极之间形成数据线，该数据线与栅极线交叉以限定一个像素区域，以及源极和漏极彼此间隔开; 去除通过源极和漏极暴露的杂质掺杂非晶硅图案的一部分，以限定欧姆接触层; 通过源极和漏极将第一激光束照射到本征非晶硅图案上，以在第一部分的两侧形成包括多晶硅的第一部分和非晶硅的第二部分的有源层; 在数据线上形成钝化层，源电极和漏电极，钝化层具有暴露漏电极的漏极接触孔; 以及在所述像素区域中的钝化层上形成像素电极，所述像素电极通过所述漏极接触孔与所述漏电极连接。

公开(公告)号：US07910414B2

公开(公告)日：2011-03-22

申请号：US12591501

申请日：2009-11-20

申请人： Hee-Dong Choi ,  Sang-Gul Lee ,  Seong-Moh Seo ,  Jun-Min Lee ,  Byung-Chul Ahn

发明人： Hee-Dong Choi ,  Sang-Gul Lee ,  Seong-Moh Seo ,  Jun-Min Lee ,  Byung-Chul Ahn

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L27/1274 ,  H01L27/1214 ,  H01L27/1288 ,  H01L29/4908

摘要： A method of fabricating an array substrate includes sequentially forming a first metal layer, a first inorganic insulating layer and an intrinsic amorphous silicon layer on a substrate, the first metal layer including a first metallic material layer and a second metallic material layer; crystallizing the intrinsic amorphous silicon; forming a gate electrode, a gate line, a gate insulating layer and an active layer; forming an interlayer insulating layer including first and second contact holes respectively exposing both sides of the active layer; forming first and second ohmic contact patterns respectively contacting the both sides of the active layers, a source electrode, a drain electrode, and a data line connecting the source electrode; forming a passivation layer on the source electrode, the drain electrode; and forming a pixel electrode on the passivation layer and contacting the drain electrode.

摘要翻译： 制造阵列基板的方法包括在基板上依次形成第一金属层，第一无机绝缘层和本征非晶硅层，所述第一金属层包括第一金属材料层和第二金属材料层; 结晶本征非晶硅; 形成栅电极，栅极线，栅绝缘层和有源层; 形成包括分别暴露有源层的两侧的第一和第二接触孔的层间绝缘层; 形成分别接触有源层的两侧的第一和第二欧姆接触图案，源电极，漏电极和连接源电极的数据线; 在源极上形成钝化层，漏电极; 以及在所述钝化层上形成像素电极并与所述漏电极接触。

公开(公告)号：US07285459B2

公开(公告)日：2007-10-23

申请号：US11063730

申请日：2005-02-24

申请人： Seong-Moh Seo ,  Jae-Bon Koo

发明人： Seong-Moh Seo ,  Jae-Bon Koo

IPC分类号： H01L21/8244 ,  H01L21/8242 ,  H01L21/339 ,  H01L21/84 ,  H01L51/00

CPC分类号： H01L29/66757 ,  H01L27/1255 ,  H01L27/1288 ,  H01L27/3244

摘要： A flat panel display device having a high capacitance and a high aperture ratio. A thin film transistor and a capacitor are formed on an insulating substrate. The thin film transistor includes a semiconductor layer, a gate electrode and source and drain electrodes. The capacitor has first and second capacitor electrodes and a dielectric layer. An insulating layer is formed over the transistor to insulate the gate electrode from the source and drain electrodes, and a portion of the insulating layer is formed as the dielectric layer between the first and second capacitor electrodes. A non-planar shape of the first capacitor electrode and a conforming shape of the dielectric layer and a second capacitor electrode increase a capacitance of the capacitor. The portion of the insulating layer serving as the capacitor dielectric is formed to be thinner than the portion of the insulating layer formed over the gate electrode.

摘要翻译： 具有高电容和高开口率的平板显示装置。 在绝缘基板上形成薄膜晶体管和电容器。 薄膜晶体管包括半导体层，栅极电极和源极和漏极。 电容器具有第一和第二电容器电极和电介质层。 在晶体管上形成绝缘层以使栅电极与源电极和漏电极绝缘，并且绝缘层的一部分形成为第一和第二电容器电极之间的电介质层。 第一电容器电极的非平面形状和电介质层和第二电容器电极的适形形状增加了电容器的电容。 用作电容器电介质的绝缘层的部分形成为比形成在栅电极上的绝缘层的部分更薄。

公开(公告)号：US20050263761A1

公开(公告)日：2005-12-01

申请号：US11124124

申请日：2005-05-09

申请人： Chang-Soo Kim ,  Tae-Wook Kang ,  Chang-Yong Jeong ,  Jae-Young Oh ,  Sang-Il Park ,  Seong-Moh Seo

发明人： Chang-Soo Kim ,  Tae-Wook Kang ,  Chang-Yong Jeong ,  Jae-Young Oh ,  Sang-Il Park ,  Seong-Moh Seo

IPC分类号： G02F1/1368 ,  G02F1/136 ,  G09F9/30 ,  H01L21/00 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L27/32 ,  H01L29/04 ,  H01L29/10 ,  H01L29/15 ,  H01L29/745 ,  H01L29/76 ,  H01L29/786 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20 ,  H01L51/52

CPC分类号： H01L29/78603 ,  H01L27/12 ,  H01L27/1248 ,  H01L27/3262 ,  H01L51/5284

摘要： A TFT having a dual buffer structure, a method of fabricating the same, and a flat panel display having the TFT, and a method of fabricating the same are provided. The TFT includes a first buffer layer formed of an amorphous silicon layer on a substrate, a second buffer layer formed on the first buffer layer. The TFT also includes a semiconductor layer formed on the second buffer layer and a gate electrode formed on the semiconductor layer. The dual buffer structure provides better barrier to impurities diffusing from the substrate, and also acts as a black matrix to reduce unwanted reflections and is a source of hydrogen to passivate other layers.

摘要翻译： 提供具有双缓冲结构的TFT及其制造方法，以及具有该TFT的平板显示器及其制造方法。 TFT包括由衬底上的非晶硅层形成的第一缓冲层，形成在第一缓冲层上的第二缓冲层。 TFT还包括形成在第二缓冲层上的半导体层和形成在半导体层上的栅电极。 双缓冲结构为从衬底扩散的杂质提供更好的屏障，并且还用作黑色矩阵以减少不必要的反射，并且是氢源来钝化其它层。

公开(公告)号：US06878584B2

公开(公告)日：2005-04-12

申请号：US10857983

申请日：2004-06-02

申请人： Seong-Moh Seo ,  Jae-Bon Koo

发明人： Seong-Moh Seo ,  Jae-Bon Koo

IPC分类号： H05B33/10 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L27/13 ,  H01L27/32 ,  H01L21/8242

CPC分类号： H01L29/66757 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1288 ,  H01L27/3244 ,  H01L27/3265

摘要： A flat panel display device having a high capacitance and a high aperture ratio. A thin film transistor and a capacitor are formed on an insulating substrate. The thin film transistor includes a semiconductor layer, a gate electrode and source and drain electrodes. The capacitor has first and second capacitor electrodes and a dielectric layer. An insulating layer is formed over the transistor to insulate the gate electrode from the source and drain electrodes, and a portion of the insulating layer is formed as the dielectric layer between the first and second capacitor electrodes. A non-planar shape of the first capacitor electrode and a conforming shape of the dielectric layer and a second capacitor electrode increase a capacitance of the capacitor. The portion of the insulating layer serving as the capacitor dielectric is formed to be thinner than the portion of the insulating layer formed over the gate electrode.

摘要翻译： 具有高电容和高开口率的平板显示装置。 在绝缘基板上形成薄膜晶体管和电容器。 薄膜晶体管包括半导体层，栅极电极和源极和漏极。 电容器具有第一和第二电容器电极和电介质层。 在晶体管上形成绝缘层以使栅电极与源电极和漏电极绝缘，并且绝缘层的一部分形成为第一和第二电容器电极之间的电介质层。 第一电容器电极的非平面形状和电介质层和第二电容器电极的适形形状增加了电容器的电容。 用作电容器电介质的绝缘层的部分形成为比形成在栅电极上的绝缘层的部分更薄。