公开(公告)号：US07869006B2

公开(公告)日：2011-01-11

申请号：US12202645

申请日：2008-09-02

Applicant: Hong Ki Kim ,  Chan Yong Park ,  Seung Won Lee ,  Sun Ki Min

Inventor： Hong Ki Kim ,  Chan Yong Park ,  Seung Won Lee ,  Sun Ki Min

IPC: G01C3/08

CPC classification number: G01B11/026 ,  G01S7/497 ,  G01S17/10

Abstract: A laser measuring device maintains high responsivity irrespective of changes in surrounding environment, provides more correct measurement and long distance measurement due to reduced noise, and ensures the safety and reliability of a product. A first light emitter emits first wavelength light having a first wavelength. A second light emitter emits second wavelength light having a second wavelength, the second light emitter being arranged perpendicular to the first light emitter. An optical mirror allows one of the first wavelength light and the second wavelength light to pass but reflecting the other one. A first band pass filter for allows the first wavelength light to pass. A second band pass filter allows the second wavelength light to pass. A light receiver receives incident light, which arrives through one of the first and second band pass filters. A controller activates at least one of the first and second light emitters.

Abstract translation: 激光测量装置保持高响应度，不管周围环境如何变化，由于噪音降低，可提供更准确的测量和长距离测量，并确保产品的安全性和可靠性。 第一发光器发射具有第一波长的第一波长光。 第二发光体发射具有第二波长的第二波长光，第二光发射器垂直于第一光发射器布置。 光学镜允许第一波长光和第二波长光中的一个通过但反射另一个。 用于允许第一波长光通过的第一带通滤波器。 第二带通滤波器允许第二波长光通过。 光接收器接收通过第一和第二带通滤波器之一到达的入射光。 控制器激活第一和第二发光体中的至少一个。

公开(公告)号：US20100241877A1

公开(公告)日：2010-09-23

申请号：US12717252

申请日：2010-03-04

Applicant: Seung Won LEE

Inventor： Seung Won LEE

IPC: G06F1/26 ,  G06F12/00

CPC classification number: G11C7/1042 ,  G11C5/145 ,  G11C5/147

Abstract: Disclosed is an integrated circuit card which includes a central processing unit (CPU); a first memory block and a second memory block configured to operate responsive to a control of the CPU; and a high voltage generator block configured to generate a high voltage to be supplied to the first and second memory blocks. When bit lines of the first memory block are set by the high voltage, the CPU controls the high voltage generator block to supply the second memory block with the high voltage for a program operation of the second memory block during the program operation of the first memory block.

Abstract translation: 公开了一种集成电路卡，其包括中央处理单元（CPU）; 第一存储器块和第二存储器块，被配置为响应于CPU的控制而操作; 以及高电压发生器模块，被配置为产生要提供给所述第一和第二存储器块的高电压。 当第一存储器块的位线被高电压设置时，CPU在第一存储器的编程操作期间控制高电压发生器块以提供具有高电压的第二存储器块用于第二存储器块的编程操作 块。

公开(公告)号：US07602223B2

公开(公告)日：2009-10-13

申请号：US11877187

申请日：2007-10-23

Applicant: Seung-Hwan Baek ,  Seung-Won Lee

Inventor： Seung-Hwan Baek ,  Seung-Won Lee

IPC: H03L7/06

CPC classification number: H03L7/0812 ,  H03L7/0891 ,  H03L7/113 ,  H03L7/16

Abstract: A delay-locked loop circuit includes: a phase detector generating a detection signal from a phase difference between an external clock signal and a feedback clock signal; a charge pump controlling a level of a voltage signal in response to the detection signal; and a voltage-controlled delay line generating a plurality of delay clock signals by delaying the external clock signal in response to the voltage signal and generating a multiplied clock signal using the delay clock signals in different numbers in accordance with a frequency domain of the external clock signal. The multiplied clock signal is generated by multiplying the external clock signal an integer number of times and the feedback clock signal is delayed from the plurality of delay clock signals by a cycle period of the external clock signal.

Abstract translation: 延迟锁定环路电路包括：相位检测器，从外部时钟信号和反馈时钟信号之间的相位差产生检测信号; 电荷泵，响应于检测信号控制电压信号的电平; 以及电压控制延迟线，通过响应于电压信号延迟外部时钟信号并且根据外部时钟的频域使用不同数量的延迟时钟信号产生倍增时钟信号来产生多个延迟时钟信号 信号。 乘法时钟信号通过将外部时钟信号乘以整数倍而产生，反馈时钟信号从多个延迟时钟信号延迟外部时钟信号的周期。

公开(公告)号：US20090233624A1

公开(公告)日：2009-09-17

申请号：US12400896

申请日：2009-03-10

Applicant: Seung Won LEE

Inventor： Seung Won LEE

IPC: H04W24/00

CPC classification number: H04M1/72544 ,  H04L67/18 ,  H04L67/306 ,  H04M1/72572 ,  H04W4/02

Abstract: A method and system for providing a mobile terminal search service includes the steps of (a) requesting, by a first mobile terminal, to search for a second mobile terminal, the first mobile terminal having avatar information stored thereon, and (b) searching for the second mobile terminal within a geographical range corresponding to the avatar information of the first mobile terminal.

Abstract translation: 一种用于提供移动终端搜索服务的方法和系统包括以下步骤：（a）由第一移动终端请求搜索第二移动终端，所述第一移动终端具有存储在其上的化身信息，以及（b）搜索 所述第二移动终端在对应于所述第一移动终端的化身信息的地理范围内。

公开(公告)号：US20090190109A1

公开(公告)日：2009-07-30

申请号：US12323807

申请日：2008-11-26

Applicant: Chun-Seok Jeong ,  Ho-Youn Park ,  Sok-Joo Lee ,  Seung-Won Lee

Inventor： Chun-Seok Jeong ,  Ho-Youn Park ,  Sok-Joo Lee ,  Seung-Won Lee

IPC: G03B27/42

CPC classification number: H01L21/67718 ,  G02F1/1303 ,  H01L21/6776

Abstract: A substrate transfer apparatus that is designo provide an inclined transfer function that improves liquid saving efficiency of a process solution (developing solution) during the transfer of the substrate. The substrate transfer apparatus includes a first transfer unit for transferring a substrate, a second transfer unit spaced apart from an end of the first transfer unit, a third transfer unit disposed between the first and second transfer units and providing an inclined transfer that is capable of saving a developing solution adhered to the substrate during transfer of the substrate, and a transfer controller for controlling an inclined transfer angle and a connection state of the third transfer unit.

Abstract translation: 一种基板转印装置，其设计提供了一种倾斜的传递函数，其在基底转印期间提高了处理溶液（显影液）的液体节省效率。 基片传送装置包括用于传送基片的第一传送单元，与第一传送单元的端部隔开的第二传送单元，设置在第一和第二传送单元之间的第三传送单元，提供能够 在基板的转印过程中节约了附着在基板上的显影液，以及用于控制第三转印单元的倾斜转印角度和连接状态的转印控制器。

公开(公告)号：US20080192560A1

公开(公告)日：2008-08-14

申请号：US11734082

申请日：2007-04-11

Applicant: Seung Won Lee ,  Ki Hong Kim ,  Sun Kwon Kim ,  Byeong Hoon Lee

Inventor： Seung Won Lee ,  Ki Hong Kim ,  Sun Kwon Kim ,  Byeong Hoon Lee

IPC: G11C8/12

CPC classification number: G11C11/412 ,  G11C7/12 ,  G11C16/0483 ,  G11C16/24 ,  G11C2207/002

Abstract: An integrated circuit memory system includes an integrated circuit device having a random access memory array, a non-volatile memory array (e.g., flash memory array) and a data transfer circuit therein. The memory arrays and data transfer circuit may be included in a common integrated circuit chip. The random access memory (RAM) array includes a plurality of columns of RAM cells and a first plurality of bit lines, which are electrically connected to the plurality of columns of RAM cells. The non-volatile memory array includes a plurality of columns of non-volatile memory cells and a second plurality of bit lines, which are electrically connected to a plurality of columns of non-volatile memory cells. The data transfer circuit is electrically connected to the first and second pluralities of bit lines. The data transfer circuit is configured to support direct bidirectional communication between the first and second pluralities of bit lines.

Abstract translation: 集成电路存储器系统包括具有随机存取存储器阵列，非易失性存储器阵列（例如闪存阵列）和其中的数据传输电路的集成电路器件。 存储器阵列和数据传输电路可以包括在公共集成电路芯片中。 随机存取存储器（RAM）阵列包括多个RAM单元列和第一多个位线，它们电连接到多个RAM单元列。 非易失性存储器阵列包括多列非易失性存储器单元和第二多个位线，其电连接到多列非易失性存储器单元。 数据传输电路电连接到第一和第二多个位线。 数据传输电路被配置为支持第一和第二多个位线之间的直接双向通信。

公开(公告)号：US20080192542A1

公开(公告)日：2008-08-14

申请号：US11764613

申请日：2007-06-18

Applicant: Byeong-Hoon Lee ,  Ki-Hong Kim ,  Seung-Won Lee ,  Sun-Kwon Kim

Inventor： Byeong-Hoon Lee ,  Ki-Hong Kim ,  Seung-Won Lee ,  Sun-Kwon Kim

IPC: G11C11/409

CPC classification number: G11C16/0483

Abstract: A memory system includes a memory and a memory controller operating to control the memory. The memory includes a random accessible memory including a memory cell array operable in a random access mode, a NAND flash memory, and a selection circuit making the memory controller operate either one of the random accessible memory or the NAND flash memory.

Abstract translation: 存储器系统包括操作以控制存储器的存储器和存储器控制器。 存储器包括随机存取存储器，其包括以随机存取模式操作的存储单元阵列，NAND闪速存储器和使存储器控制器操作随机存取存储器或NAND闪速存储器之一的选择电路。

公开(公告)号：US20080189474A1

公开(公告)日：2008-08-07

申请号：US11761620

申请日：2007-06-12

Applicant: Ki-Hong Kim ,  Byeong-Hoon Lee ,  Seung-Won Lee ,  Sun-Kwon Kim

Inventor： Ki-Hong Kim ,  Byeong-Hoon Lee ,  Seung-Won Lee ,  Sun-Kwon Kim

IPC: G06F12/00

CPC classification number: G11C16/20

Abstract: A memory card includes: a first memory chip responding to all commands input externally; and a second memory chip responding to commands, among the commands input externally, relevant to reading, programming, and erasing operations with data. Card identification information stored in the first memory chip includes capacity information corresponding to a sum of sizes of the first and second memory chips. The plurality of memory chips of the memory card are useful in designing the memory card with storage capacity in various forms.

Abstract translation: 存储卡包括：响应于外部输入的所有命令的第一存储器芯片; 以及响应命令的第二存储器芯片，在外部输入的命令中与数据的读取，编程和擦除操作相关。 存储在第一存储器芯片中的卡识别信息包括对应于第一和第二存储器芯片的尺寸之和的容量信息。 存储卡的多个存储芯片可用于以各种形式设计具有存储容量的存储卡。

公开(公告)号：US20080093465A1

公开(公告)日：2008-04-24

申请号：US11763856

申请日：2007-06-15

Applicant: Seung-Won LEE

Inventor： Seung-Won LEE

IPC: G06K19/07

CPC classification number: G06K19/07 ,  G01R31/3187 ,  G06K7/0095 ,  G11C16/04 ,  G11C29/16 ,  G11C2029/0401 ,  G11C2029/1208

Abstract: A smart card includes a non-volatile memory, a CPU, and a plurality of pads. The non-volatile memory stores a test program. The CPU is released from a reset state in response to a test enable signal. The CPU executes the test program stored in the non-volatile memory based on predetermined flag information and stores a result of the test program in the non-volatile memory.

Abstract translation: 智能卡包括非易失性存储器，CPU和多个焊盘。 非易失性存储器存储测试程序。 响应于测试使能信号，CPU从复位状态释放。 CPU基于预定的标志信息执行存储在非易失性存储器中的测试程序，并将测试程序的结果存储在非易失性存储器中。

公开(公告)号：US07298190B2

公开(公告)日：2007-11-20

申请号：US11247938

申请日：2005-10-11

Applicant: Seung-won Lee ,  Hwi-taek Chung ,  Byeong-hoon Lee

Inventor： Seung-won Lee ,  Hwi-taek Chung ,  Byeong-hoon Lee

IPC: H03L7/06

CPC classification number: H03L7/0995 ,  H03L7/0891 ,  H03L7/099 ,  H03L7/10 ,  H03L7/18 ,  H03L2207/06

Abstract: A phase locked loop (PLL) integrated circuit includes a voltage-controlled oscillator (VCO) configured to generate a clock signal at an output terminal thereof. The VCO is further configured to improve the frequency response of the PLL by varying a capacitance of the output terminal concurrently with changing a frequency of the clock signal. The VCO may include a control signal generator, which is configured to generate a plurality of control signals in response to UP and DOWN pumping signals, and an oscillator, which is configured to generate the clock signal in response to the plurality of control signals. The oscillator may be a ring oscillator, which is responsive to the plurality of control signals.

Abstract translation: 锁相环（PLL）集成电路包括被配置为在其输出端产生时钟信号的压控振荡器（VCO）。 VCO还被配置为通过改变输出端的电容同时改变时钟信号的频率来改善PLL的频率响应。 VCO可以包括控制信号发生器，其被配置为响应于UP和DOWN泵浦信号而产生多个控制信号，以及振荡器，其被配置为响应于多个控制信号而产生时钟信号。 振荡器可以是响应于多个控制信号的环形振荡器。