公开(公告)号：US6108243A

公开(公告)日：2000-08-22

申请号：US383014

申请日：1999-08-25

申请人： Takaaki Suzuki ,  Shinya Fujioka ,  Yasuharu Sato

发明人： Takaaki Suzuki ,  Shinya Fujioka ,  Yasuharu Sato

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  G11C7/00

CPC分类号： G11C7/22 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/1072 ,  G11C2207/2281 ,  G11C2207/229

摘要： The present invention is an FCRAM comprising a first stage for performing command decoding, a second stage for performing sense amplifier activation, and a third stage for performing data input and output, configured in a pipeline structure, a plurality of data bits being transferred in parallel between the sense amplifiers and the third stage, wherein sense amplifiers are deactivated automatically and a reset operation is performed after data has been transferred in parallel between sense amplifiers and the third stage, in response to a standard read or write command.

摘要翻译： 本发明是一种FCRAM，包括用于执行命令解码的第一级，用于执行读出放大器激活的第二级，以及在流水线结构中执行数据输入和输出的第三级，并行传输的多个数据位 在读出放大器和第三级之间，其中读出放大器被自动去激活，并且在数据已经在感测放大器和第三级之间并行传送之后，响应于标准的读或写命令来执行复位操作。

公开(公告)号：US6088291A

公开(公告)日：2000-07-11

申请号：US147600

申请日：1999-01-29

申请人： Shinya Fujioka ,  Masao Taguchi ,  Waichirou Fujieda ,  Yasuharu Sato ,  Takaaki Suzuki ,  Tadao Aikawa ,  Takayuki Nagasawa

发明人： Shinya Fujioka ,  Masao Taguchi ,  Waichirou Fujieda ,  Yasuharu Sato ,  Takaaki Suzuki ,  Tadao Aikawa ,  Takayuki Nagasawa

IPC分类号： G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4094 ,  G11C7/00

CPC分类号： G11C7/06 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4094 ,  G11C7/1039 ,  G11C7/1072 ,  G11C7/12 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C2207/005 ,  G11C2207/065

摘要： The present invention is aimed at providing a semiconductor memory device which performs a row-address pipe-line operation in accessing different row addresses so as to achieve high-speed access. The semiconductor memory device according to the present invention includes a plurality of sense-amplifiers which store data when the data is received via bit lines from memory cells corresponding to a selected word line, a column decoder which reads parallel data of a plurality of bits from selected sense amplifiers by simultaneously selecting a plurality of column gates in response to a column address, a data-conversion unit which converts the parallel data into serial data, and a precharge-signal-generation unit which generates an internal precharge signal a first delay-time period after generation of a row-access signal for selecting the selected word line so as to reset the bit lines and said plurality of sense-amplifiers.

摘要翻译： PCT No.PCT / JP98 / 02443 Sec。 371日期1999年1月29日第 102（e）日期1999年1月29日PCT提交1998年6月3日PCT公布。 第WO98 / 56004号公报 日期：1998年12月10日本发明旨在提供一种在访问不同行地址时执行行地址管线操作以实现高速访问的半导体存储器件。 根据本发明的半导体存储器件包括多个读出放大器，当经由位线从存储器单元接收数据时存储数据，该存储器单元对应于所选择的字线，列解码器从多个位读取多个位的并行数据 选择的读出放大器，通过响应于列地址同时选择多个列门，将并行数据转换为串行数据的数据转换单元，以及产生内部预充电信号的预充电信号产生单元， 生成用于选择所选字线的行访问信号以便复位位线和所述多个感测放大器之后的时间段。

公开(公告)号：US5668763A

公开(公告)日：1997-09-16

申请号：US606819

申请日：1996-02-26

申请人： Shinya Fujioka ,  Atsushi Hatakeyama ,  Hirohiko Mochizuki

发明人： Shinya Fujioka ,  Atsushi Hatakeyama ,  Hirohiko Mochizuki

IPC分类号： G11C29/00

CPC分类号： G11C29/808

摘要： A semiconductor memory has a plurality of memory arrays, and a plurality of selection circuits. Each of the memory arrays has a plurality of memory blocks. The selection circuits is provided to the memory arrays and is used to independently disable a defective memory block and select a normal memory block in the memory array. Therefore, the semiconductor memory enables to increase the number of partial good memories (half good memories: half capacity memory), and to increase a product yield.

摘要翻译： 半导体存储器具有多个存储器阵列和多个选择电路。 每个存储器阵列具有多个存储器块。 选择电路被提供给存储器阵列，并且用于独立地禁用缺陷存储器块并选择存储器阵列中的正常存储器块。 因此，半导体存储器能够增加部分良好存储器的数量（半好的存储器：半容量存储器），并且增加产品产量。

公开(公告)号：US20130182559A1

公开(公告)日：2013-07-18

申请号：US13553631

申请日：2012-07-19

申请人： Shinya Fujioka ,  Yoshihiro Ashi ,  Masahiko Mizutani ,  Hideki Endo

发明人： Shinya Fujioka ,  Yoshihiro Ashi ,  Masahiko Mizutani ,  Hideki Endo

IPC分类号： H04L12/24

CPC分类号： H04L41/0668 ,  H04L43/0817

摘要： A transmission network is comprised of a network management system for collectively managing and controlling a plurality of transmission devices coupled mutually through transmission routes and the transmission network as well. The network management system includes a plane management table adapted to manage transmission planes defined as a set of paths in the transmission network, and the plane management table has the function to set and manage a transmission plane (working plane) applied during normal operation and besides, a single or a plurality of transmission planes (protection planes) applicable in the event of occurrence of a fault in the transmission network. Then, when a fault occurs in the transmission network, the network management system changes the applied plane to a suitable transmission plane.

公开(公告)号：US07746718B2

公开(公告)日：2010-06-29

申请号：US11998428

申请日：2007-11-30

申请人： Yasuyuki Eguchi ,  Shinya Fujioka ,  Yoshiaki Okuyama

发明人： Yasuyuki Eguchi ,  Shinya Fujioka ,  Yoshiaki Okuyama

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C8/12 ,  G11C11/40622

摘要： A refresh register stores disable block information indicating a memory block whose refresh operation is to be disabled. A refresh control circuit periodically executes the refresh operation of a memory block except the memory block corresponding to the disable block information. During an access cycle to one of the memory blocks, the register control circuit writes the disable block information to the refresh register according to an external input. Consequently, in order to rewrite the refresh register, it is not necessary to use an additional operation cycle to the access cycle. Since there is no need to insert an extra operation cycle, it is possible to change a memory area to be refreshed without lowering effective efficiency of access cycles. As a result, power consumption can be reduced.

摘要翻译： 刷新寄存器存储指示将被禁用刷新操作的存储器块的禁止块信息。 刷新控制电路周期性地执行除了与禁用块信息相对应的存储块之外的存储器块的刷新操作。 在对存储器块之一的访问周期期间，寄存器控制电路根据外部输入将该禁止块信息写入刷新寄存器。 因此，为了重写刷新寄存器，不需要对访问周期使用附加的操作周期。 由于不需要插入额外的操作周期，因此可以改变要刷新的存储器区域，而不会降低访问周期的有效效率。 结果，可以降低功耗。

公开(公告)号：US07483323B2

公开(公告)日：2009-01-27

申请号：US11515853

申请日：2006-09-06

申请人： Shinya Fujioka ,  Tomohiro Kawakubo ,  Koichi Nishimura ,  Kotoku Sato

发明人： Shinya Fujioka ,  Tomohiro Kawakubo ,  Koichi Nishimura ,  Kotoku Sato

IPC分类号： G11C7/00 ,  G11C5/14

CPC分类号： G06F1/3234 ,  G06F1/3203 ,  G06F1/3268 ,  G06F1/3275 ,  G11C5/14 ,  G11C5/145 ,  G11C5/147 ,  G11C11/406 ,  G11C11/40615 ,  G11C14/00 ,  G11C2207/2227 ,  G11C2211/4067 ,  H02M3/07 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

摘要： An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.

公开(公告)号：US20080144417A1

公开(公告)日：2008-06-19

申请号：US11998428

申请日：2007-11-30

申请人： Yasuyuki Eguchi ,  Shinya Fujioka ,  Yoshiaki Okuyama

发明人： Yasuyuki Eguchi ,  Shinya Fujioka ,  Yoshiaki Okuyama

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C11/406 ,  G11C8/12 ,  G11C11/40622

摘要： A refresh register stores disable block information indicating a memory block whose refresh operation is to be disabled. A refresh control circuit periodically executes the refresh operation of a memory block except the memory block corresponding to the disable block information. During an access cycle to one of the memory blocks, the register control circuit writes the disable block information to the refresh register according to an external input. Consequently, in order to rewrite the refresh register, it is not necessary to use an additional operation cycle to the access cycle. Since there is no need to insert an extra operation cycle, it is possible to change a memory area to be refreshed without lowering effective efficiency of access cycles. As a result, power consumption can be reduced.

摘要翻译： 刷新寄存器存储指示将被禁用刷新操作的存储器块的禁止块信息。 刷新控制电路周期性地执行除了与禁用块信息相对应的存储块之外的存储器块的刷新操作。 在对存储器块之一的访问周期期间，寄存器控制电路根据外部输入将该禁止块信息写入刷新寄存器。 因此，为了重写刷新寄存器，不需要对访问周期使用附加的操作周期。 由于不需要插入额外的操作周期，因此可以改变要刷新的存储区域，而不会降低访问周期的有效效率。 结果，可以降低功耗。

公开(公告)号：US20070002664A1

公开(公告)日：2007-01-04

申请号：US11515852

申请日：2006-09-06

申请人： Shinya Fujioka ,  Tomohiro Kawakubo ,  Koichi Nishimura ,  Kotoku Sato

发明人： Shinya Fujioka ,  Tomohiro Kawakubo ,  Koichi Nishimura ,  Kotoku Sato

IPC分类号： G11C5/14

CPC分类号： G06F1/3234 ,  G06F1/3203 ,  G06F1/3268 ,  G06F1/3275 ,  G11C5/14 ,  G11C5/145 ,  G11C5/147 ,  G11C11/406 ,  G11C11/40615 ,  G11C14/00 ,  G11C2207/2227 ,  G11C2211/4067 ,  H02M3/07 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

摘要： An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.

公开(公告)号：US20060291307A1

公开(公告)日：2006-12-28

申请号：US11260486

申请日：2005-10-28

申请人： Shinya Fujioka ,  Yoshiaki Okuyama ,  Yasuhiro Takada ,  Tatsuhiro Watanabe ,  Nobumi Kodama

发明人： Shinya Fujioka ,  Yoshiaki Okuyama ,  Yasuhiro Takada ,  Tatsuhiro Watanabe ,  Nobumi Kodama

IPC分类号： G11C29/00

CPC分类号： G11C29/06 ,  G11C29/10 ,  G11C2029/0405 ,  G11C2029/1204 ,  G11C2029/3602

摘要： A burn-in test, including first to sixth steps where voltages are applied for the same lengths of time in each step, is applied to a semiconductor memory having alternately arranged bit line pairs with twist structure where the bit lines cross each other and bit line pairs with non-twist structure where the bit lines are parallel to each other. Since lengths of time in which a stress is applied for all bit lines can be equally set, no deviation occurs in lengths of time where stress is applied between the bit lines. Characteristics of memory cells can be prevented from excessively deteriorating from the burn-in test. Further, the number of bit lines not having stress applied can be minimized in the first to sixth steps. Accordingly, the ratio of the bit lines having stress applied can be increased, which reduces the burn-in test time. Thus, test cost can be reduced.

摘要翻译： 包括在每个步骤中施加相同时间长度的电压的第一至第六步骤的老化测试被施加到具有交替排列的位线对的半导体存储器，其中位线彼此交叉并且位线 对，其中位线彼此平行的非扭转结构。 由于可以对所有位线施加应力的时间长度，所以在位线之间施加应力的时间长度不会发生偏差。 可以防止记忆单元的特性从老化测试过度恶化。 此外，在第一至第六步骤中可以使不具有应力的位线的数量最小化。 因此，可以增加施加了应力的位线的比例，这降低了老化测试时间。 因此，可以降低测试成本。

公开(公告)号：US20050185497A1

公开(公告)日：2005-08-25

申请号：US11114087

申请日：2005-04-26

申请人： Hitoshi Ikeda ,  Shinya Fujioka ,  Takahiro Sawamura

发明人： Hitoshi Ikeda ,  Shinya Fujioka ,  Takahiro Sawamura

IPC分类号： G11C7/10 ,  G11C8/00 ,  G11C8/08 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/408

CPC分类号： G11C8/08 ,  G11C7/1018 ,  G11C7/1042 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4085

摘要： A word control circuit activates word lines corresponding to a start row address and a next row address overlappingly in the continuous mode. Accordingly, even in the case where the start address indicates an end memory cell connected to a word line, the switching operation of the word line becomes unnecessary. Memory cells connected to different word lines can be thus accessed in a sequential manner. That is, a controller accessing a semiconductor memory device can access the memory without data interruption. This can prevent the data transfer rate from lowering. Furthermore, it is made unnecessary to form a signal and a control circuit for informing a controller of the fact that a word line is being switched so that the construction of a semiconductor memory device and a control circuit of the controller can be simplified. This results in reduction of the system cost.

摘要翻译： 字控制电路在连续模式下重叠地起动对应于起始行地址和下一行地址的字线。 因此，即使在开始地址指示连接到字线的结束存储单元的情况下，也不需要字线的切换操作。 可以按顺序的方式访问连接到不同字线的存储单元。 也就是说，访问半导体存储器件的控制器可以访问存储器而没有数据中断。 这可以防止数据传输速率降低。 此外，不需要形成信号和控制电路，用于通知控制器正在切换字线的事实，使得可以简化控制器的半导体存储器件和控制电路的结构。 这导致系统成本的降低。