公开(公告)号：US07065601B2

公开(公告)日：2006-06-20

申请号：US10456860

申请日：2003-06-06

Applicant: Stuart Ryan ,  Andrew Jones

Inventor： Stuart Ryan ,  Andrew Jones

IPC: G06F13/14

CPC classification number: G06F13/385 ,  G06F13/24 ,  G06F2213/0038

Abstract: An interface is described which has at least one chip side port with a first plurality of pins for conveying fields of a packet and first and second circuit side ports each port having a set of pins with a lower number than the first set of pins in the chip side port. The interface is constructed so that interrupt signals from an off-chip circuit can be conveyed on-chip in a manner such that the interrupt signals are indistinguishable from interrupt signals received from on-chip modules connected to an on-chip communication path. The same principle is applicable to power-down signals.

公开(公告)号：US20050015565A1

公开(公告)日：2005-01-20

申请号：US10621012

申请日：2003-07-15

Applicant: Stuart Ryan ,  Andrew Jones

Inventor： Stuart Ryan ,  Andrew Jones

IPC: G06F12/02 ,  G06F12/08

CPC classification number: G06F12/0292

Abstract: A prototype system is described having an integrated circuit including an on-chip processor and an on-chip router connected to off-chip resources via an interface. A request directing unit on the chip receives memory access requests and directs them in accordance with either one of two address maps. In one of the address maps, a first range of addresses is allocated to at least one on-chip resource and a second range of addresses is allocated to the interface. In the other memory address map, the first range of addresses is also allocated to the interface. An integrated circuit including such a request directing unit is also described, together with a method for evaluating a prototype system.

Abstract translation: 描述了一种具有包括片上处理器和通过接口连接到片外资源的片上路由器的集成电路的原型系统。 芯片上的请求引导单元接收存储器访问请求，并根据两个地址映射中的任一个引导它们。 在一个地址映射中，将第一范围的地址分配给至少一个片上资源，并且将第二范围的地址分配给该接口。 在另一个存储器地址映射中，第一个地址范围也被分配给接口。 还描述了包括这种请求引导单元的集成电路以及用于评估原型系统的方法。

公开(公告)号：US20190335455A1

公开(公告)日：2019-10-31

申请号：US16349383

申请日：2017-11-14

Applicant: Peter Jonathon ,  Stuart RYAN ,  Bluwireless Technology Limited

Inventor： Peter Jonathon LEGG ,  Stuart RYAN

IPC: H04W72/04 ,  H04W28/02

Abstract: An apparatus schedules communications in a wireless communication system comprising a plurality of wireless stations (103-107) operable to communicate wirelessly with each other in accordance with a time division multiple access scheme. The apparatus comprises a receiver (303) for receiving resource requests from the plurality of wireless stations (103-107). A scheduler (305) schedules air interface resource to communications between the plurality wireless stations by allocating time intervals in repeating scheduling intervals. A transmitter (301) transmits scheduling messages providing indications of the scheduling to the plurality of wireless stations (103-107). An adapter (307) adapts a duration of at least one scheduling interval of the repeating scheduling intervals in response to the resource requests from the plurality of wireless stations (103-107).

公开(公告)号：US09367517B2

公开(公告)日：2016-06-14

申请号：US12958744

申请日：2010-12-02

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: G06F15/78 ,  H04L12/933

CPC classification number: G06F15/78 ,  H01L2224/16225 ,  H01L2924/15311 ,  H04L49/101 ,  H04L49/109 ,  Y02D10/12 ,  Y02D10/13

Abstract: A package includes a first die and a second die. The dies are connected to each other through an interface. At least one of the first and second dies includes a plurality of signal sources, wherein each source has at least one quality of service parameter associated therewith, and a plurality of queues having a different priorities. A signal from a respective one of the signal sources is allocated to one of the plurality of queues in dependence on the at least one quality of service parameter associated with the respective signal source. The interface is configured such that signals from said queues are transported from one of said first and second dies to the other of said first and second dies.

Abstract translation: 包装包括第一模具和第二模具。 模具通过接口彼此连接。 第一和第二裸片中的至少一个包括多个信号源，其中每个源具有与其相关联的至少一个服务质量参数，以及具有不同优先级的多个队列。 根据与相应信号源相关联的至少一个服务质量参数，来自相应信号源的信号被分配给多个队列中的一个。 接口被配置成使得来自所述队列的信号从所述第一和第二管芯中的一个传送到所述第一和第二管芯中的另一个。

公开(公告)号：US09058283B2

公开(公告)日：2015-06-16

申请号：US13560559

申请日：2012-07-27

Applicant: Stuart Ryan ,  Andrew Michael Jones

Inventor： Stuart Ryan ,  Andrew Michael Jones

IPC: G06F12/00 ,  G06F12/08

CPC classification number: G06F12/0897 ,  G06F12/0802 ,  G06F12/0811 ,  G06F12/0862 ,  G06F2212/6022

Abstract: A first cache arrangement including an input configured to receive a memory request from a second cache arrangement; a first cache memory for storing data; an output configured to provide a response to the memory request for the second cache arrangement; and a first cache controller; the first cache controller configured such that for the response to the memory request output by the output, the cache memory includes no allocation for data associated with the memory request.

Abstract translation: 一种第一高速缓存装置，包括被配置为从第二高速缓存装置接收存储器请求的输入; 用于存储数据的第一高速缓冲存储器; 输出，被配置为提供对所述第二高速缓存装置的所述存储器请求的响应; 和第一缓存控制器; 第一缓存控制器被配置为使得对于由输出输出的存储器请求的响应，高速缓存存储器不包括与存储器请求相关联的数据的分配。

公开(公告)号：US08347258B2

公开(公告)日：2013-01-01

申请号：US13028250

申请日：2011-02-16

Applicant: Ignazio Antonino Urzi ,  Philippe D'Audigier ,  Olivier Sauvage ,  Stuart Ryan ,  Andrew Michael Jones

Inventor： Ignazio Antonino Urzi ,  Philippe D'Audigier ,  Olivier Sauvage ,  Stuart Ryan ,  Andrew Michael Jones

IPC: G06F17/50

CPC classification number: G09G5/006 ,  G06F3/14 ,  Y02T10/82

Abstract: A package includes a die and at least one further die. The die has an interface configured to receive a transaction request from the further die via an interconnect and to transmit a response to the transaction request to said further die via the interconnect. The die also has mapping circuitry which is configured to allocate to the received transaction a local source identity information as source identity information, the local source identity information comprising one of a set of reusable local source identity information. This ensures the order of transactions tagged with a same original source identity and target and allows transactions tagged with different source identifiers to be processed out of order.

Abstract translation: 包装包括模具和至少一个另外的模具。 管芯具有被配置为经由互连从另外的管芯接收事务请求并且经由互连将对事务请求的响应发送到所述另外管芯的接口。 管芯还具有映射电路，其被配置为向接收到的事务分配本地源身份信息作为源身份信息，本地源身份信息包括一组可重用的本地源身份信息。 这样可确保以相同原始来源身份和目标标记的事务的顺序，并允许以不同的源标识符标记的事务处理不正常。

公开(公告)号：US20110261603A1

公开(公告)日：2011-10-27

申请号：US12958646

申请日：2010-12-02

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: G11C5/06

CPC classification number: G06F13/4265 ,  G06F13/385 ,  H01L2224/16225 ,  H01L2924/15311 ,  Y02D10/14 ,  Y02D10/151

Abstract: A package includes a first die and a second die, at least one of said first and second dies being a memory. The dies are connected to each other through an interface. The interface is configured to transport a plurality of control signals. The number of control signals is greater than a width of the interface. At least one of the first and second dies performs a configurable grouping so as to provide a plurality of groups of control signals. The signals within a group are transmitted across the interface together.

Abstract translation: 包装包括第一管芯和第二管芯，所述第一和第二管芯中的至少一个是存储器。 模具通过接口彼此连接。 接口被配置为传送多个控制信号。 控制信号的数量大于接口的宽度。 第一和第二模具中的至少一个模具执行可配置分组，以便提供多组控制信号。 组内的信号一起通过接口传输。

公开(公告)号：US20110138093A1

公开(公告)日：2011-06-09

申请号：US12960713

申请日：2010-12-06

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: G06F13/24 ,  G06F12/00

CPC classification number: G06F13/24 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A package includes a first die and a second die. The dies are connected to each other through an interface. The package includes interrupt processing for detecting interrupt information and providing a packet in response to the interrupt information detection. The packet includes an address to which data in the packet is to be written. The interface is configured to transport the packet between the dies. A data store is provided to which the data is writable. An interrupt event is determined from data received in several packets.

Abstract translation: 包装包括第一模具和第二模具。 模具通过接口彼此连接。 该包装包括用于检测中断信息的中断处理和响应于中断信息检测提供分组。 分组包括要写入分组中的数据的地址。 该接口被配置为在信元之间传送数据包。 提供数据可写入的数据存储。 从几个数据包中接收的数据确定中断事件。

公开(公告)号：US20110133825A1

公开(公告)日：2011-06-09

申请号：US12958639

申请日：2010-12-02

Applicant: Andrew Michael Jones ,  Stuart Ryan ,  Alberto Scandurra

Inventor： Andrew Michael Jones ,  Stuart Ryan ,  Alberto Scandurra

IPC: H01L25/00

CPC classification number: G06F13/385 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: A package includes a first die and a second die, at least one of said first and second dies being a memory. The dies are connected to each other through an interface. The interface is configured to transport both control signals and memory transactions. A sampling circuit samples the control signals before transport on the interface. The sampling circuit is controlled in dependence on at least one quality of service parameter associated with a respective control signal.

Abstract translation: 包装包括第一管芯和第二管芯，所述第一和第二管芯中的至少一个是存储器。 模具通过接口彼此连接。 接口配置为传输控制信号和存储器事务。 采样电路在接口传输之前对控制信号进行采样。 取决于与相应控制信号相关联的至少一个服务质量参数来控制采样电路。

公开(公告)号：US09208096B2

公开(公告)日：2015-12-08

申请号：US12284332

申请日：2008-09-19

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F12/0846 ,  G06F12/0853 ,  G06F12/0895 ,  G06F2212/6024 ,  G06F2212/6028

Abstract: Systems and methods for pre-fetching data are disclosed that use a cache memory for storing a copy of data stored in a system memory and mechanism to initiate a pre-fetch of data from the system memory into the cache memory. The system further comprises an event monitor for monitoring events that is connected to a path on which signals representing an event are transmitted between one or more event generating modules and a processor. In some embodiments, the event monitor initiates a pre-fetch of a portion of data in response to the event monitor detecting an event indicating the availability of the portion of data in the system memory.

Abstract translation: 公开了用于预取数据的系统和方法，其使用高速缓冲存储器来存储存储在系统存储器中的数据副本和机制，以发起从系统存储器预取数据到高速缓冲存储器中。 该系统还包括事件监视器，用于监视连接到一个路径上的事件，在该路径上，在一个或多个事件生成模块和处理器之间传送表示事件的信号。 在一些实施例中，响应于事件监视器检测指示系统存储器中的数据部分的可用性的事件，事件监视器启动对部分数据的预取。