公开(公告)号：US20070212797A1

公开(公告)日：2007-09-13

申请号：US11715441

申请日：2007-03-08

Applicant: Suk-Hun Choi ,  Jang-Eun Heo ,  Yoon-Ho Son ,  Chang-Ki Hong ,  Yong-Ju Jung ,  Hwa-Young Ko ,  Dong-Hyun Im

Inventor： Suk-Hun Choi ,  Jang-Eun Heo ,  Yoon-Ho Son ,  Chang-Ki Hong ,  Yong-Ju Jung ,  Hwa-Young Ko ,  Dong-Hyun Im

IPC: H01L21/00

CPC classification number: H01L27/11502 ,  H01L27/11507 ,  H01L28/55

Abstract: A method of forming a ferroelectric device includes forming a ferroelectric pattern on a substrate, the ferroelectric pattern including a ferroelectric material including titanium and oxygen, forming an insulating layer on the ferroelectric pattern, and planarizing the insulating layer using a slurry until the ferroelectric pattern is exposed, wherein the ferroelectric pattern serves as a polishing stop pattern and the slurry includes ceria.

Abstract translation: 形成铁电体元件的方法包括在基板上形成强电介质图案，所述强电介质图案包括包含钛和氧的铁电材料，在铁电图案上形成绝缘层，并且使用浆料平坦化绝缘层，直到铁电图案为 暴露，其中铁电图案用作抛光停止图案，并且浆料包括二氧化铈。

公开(公告)号：US20070020799A1

公开(公告)日：2007-01-25

申请号：US11428925

申请日：2006-07-06

Applicant: Suk-Hun CHOI ,  Chang-Ki HONG ,  Yoon-Ho SON ,  Jang-Eun HEO

Inventor： Suk-Hun CHOI ,  Chang-Ki HONG ,  Yoon-Ho SON ,  Jang-Eun HEO

IPC: H01L21/00 ,  H01L21/06 ,  H01L21/4763

CPC classification number: H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/1683

Abstract: In methods of manufacturing a variable resistance structure and a phase-change memory device, after forming a first insulation layer on a substrate having a contact region, a contact hole exposing the contact region is formed through the first insulation layer. After forming a first conductive layer on the first insulation layer to fill up the contact hole, a first protection layer pattern is formed on the first conductive layer. The first conductive layer is partially etched to form a contact and to form a pad on the contact. A second protection layer is formed on the first protection layer pattern, and then an opening exposing the pad is formed through the second protection layer and the first protection layer pattern. After formation of a first electrode, a phase-change material layer pattern and a second electrode are formed on the first electrode and the second protection layer.

Abstract translation: 在制造可变电阻结构和相变存储器件的方法中，在具有接触区域的基板上形成第一绝缘层之后，通过第一绝缘层形成暴露接触区域的接触孔。 在第一绝缘层上形成第一导电层以填充接触孔之后，在第一导电层上形成第一保护层图案。 部分地蚀刻第一导电层以形成接触并在接触件上形成焊盘。 在第一保护层图案上形成第二保护层，然后通过第二保护层和第一保护层图案形成露出焊盘的开口。 在形成第一电极之后，在第一电极和第二保护层上形成相变材料层图案和第二电极。

公开(公告)号：US20060263909A1

公开(公告)日：2006-11-23

申请号：US11326485

申请日：2006-01-05

Applicant: Suk-Hun Choi ,  Byoung-Jae Bae ,  Yoon-Ho Son ,  Chang-Ki Hong ,  Jeong-Heon Park

Inventor： Suk-Hun Choi ,  Byoung-Jae Bae ,  Yoon-Ho Son ,  Chang-Ki Hong ,  Jeong-Heon Park

IPC: H01L21/00 ,  H01L21/8242

CPC classification number: H01L27/11507 ,  G11C11/22 ,  H01L27/11502 ,  H01L28/55 ,  H01L28/75

Abstract: Methods of forming ferroelectric layers include forming a ferroelectric layer on a substrate and chemically-mechanically polishing a surface of the ferroelectric layer by rotating a polishing pad on the surface at a rotation speed in a range from about 5 rpm to about 25 rpm. This polishing step includes pressing the polishing pad onto the surface of the ferroelectric layer at a pressure in a range from about 0.5 psi to about 3 psi. This polishing step may be followed by the step of exposing the polished surface to a rapid thermal anneal. This anneal can be performed in an inert atmosphere containing a gas selected from a group consisting of nitrogen, helium, argon and neon.

Abstract translation: 形成铁电体层的方法包括在基板上形成铁电层，并以大约5rpm至大约25rpm的旋转速度旋转表面上的抛光垫，对铁电层的表面进行化学机械抛光。 该抛光步骤包括在约0.5psi至约3psi范围内的压力下将抛光垫压在铁电层的表面上。 该抛光步骤之后可以将抛光表面暴露于快速热退火的步骤。 该退火可以在含有选自氮，氦，氩和氖的气体的惰性气氛中进行。

公开(公告)号：US20060263289A1

公开(公告)日：2006-11-23

申请号：US11419986

申请日：2006-05-23

Applicant: Jang-Eun HEO ,  Moon-Sook LEE ,  Young-Moon CHOI ,  In-Gyu BAEK ,  Yoon-Ho SON ,  Suk-Hun CHOI ,  Kyung-Rae BYUN

Inventor： Jang-Eun HEO ,  Moon-Sook LEE ,  Young-Moon CHOI ,  In-Gyu BAEK ,  Yoon-Ho SON ,  Suk-Hun CHOI ,  Kyung-Rae BYUN

IPC: D01F9/12

CPC classification number: G11C13/025 ,  B82Y10/00 ,  G11C13/0002 ,  G11C2213/35 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1675

Abstract: Disclosed is a metal-metal oxide resistive memory device including a lower conductive layer pattern disposed in a substrate. An insulation layer is formed over the substrate, including a contact hole to partially expose the upper surface of the lower conductive layer pattern. The contact hole is filled with a carbon nanotube grown from the lower conductive layer pattern. An upper electrode and a transition-metal oxide layer made of a 2-components material are formed over the carbon nanotube and the insulation layer. The metal-metal oxide resistive memory device is adaptable to high integration and operable with relatively small power consumption by increasing the resistance therein.

公开(公告)号：US20050127347A1

公开(公告)日：2005-06-16

申请号：US10999103

申请日：2004-11-29

Applicant: Suk-Hun Choi ,  Yoon-Ho Son ,  Sung-Lae Cho ,  Joon-Sang Park

Inventor： Suk-Hun Choi ,  Yoon-Ho Son ,  Sung-Lae Cho ,  Joon-Sang Park

IPC: H01L21/4763 ,  H01L21/768 ,  H01L27/24 ,  H01L29/40

CPC classification number: H01L21/76816 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76883 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126

Abstract: A protection layer is formed on a semiconductor substrate having a cell array region and an alignment key region. A plurality of data storage elements are formed on the protection layer in the cell array region. An insulating layer is formed on the data storage elements, a barrier layer is formed on the insulating layer, and a sacrificial layer is formed on the barrier layer. The sacrificial layer, the barrier layer and the insulating layer are patterned to form contact holes that expose the data storage elements, and conductive plugs are formed in the contact holes. The sacrificial layer is etched to leave portions of the conductive plugs protruding from the barrier layer. The protruding portions of the conductive plugs are removed by polishing.

Abstract translation: 在具有单元阵列区域和对准键区域的半导体基板上形成保护层。 在单元阵列区域的保护层上形成多个数据存储元件。 在数据存储元件上形成绝缘层，在绝缘层上形成阻挡层，在势垒层上形成牺牲层。 牺牲层，阻挡层和绝缘层被图案化以形成暴露数据存储元件的接触孔，并且在接触孔中形成导电插塞。 蚀刻牺牲层以使导电塞从阻挡层突出的部分。 通过抛光去除导电塞的突出部分。

公开(公告)号：US20110189851A1

公开(公告)日：2011-08-04

申请号：US13016228

申请日：2011-01-28

Applicant: Jun-Ho JEONG ,  Jang-Eun Lee ,  Se-Chung Oh ,  Suk-Hun Choi ,  Jea-Hyoung Lee ,  Woo-Jin Kim ,  Woo-Chang Lim

Inventor： Jun-Ho JEONG ,  Jang-Eun Lee ,  Se-Chung Oh ,  Suk-Hun Choi ,  Jea-Hyoung Lee ,  Woo-Jin Kim ,  Woo-Chang Lim

IPC: H01L21/28

CPC classification number: H01L21/28

Abstract: A method of fabricating a semiconductor device, the method including providing a substrate; forming an underlying layer on the substrate; forming a sacrificial layer on the underlying layer; forming an opening in the sacrificial layer by patterning the sacrificial layer such that the opening exposes a predetermined region of the underlying layer; forming a mask layer in the opening; forming an oxide mask by partially or completely oxidizing the mask layer; removing the sacrificial layer; and etching the underlying layer using the oxide mask as an etch mask to form an underlying layer pattern.

Abstract translation: 一种制造半导体器件的方法，所述方法包括提供衬底; 在衬底上形成下层; 在下层上形成牺牲层; 通过图案化所述牺牲层在所述牺牲层中形成开口，使得所述开口暴露所述下层的预定区域; 在开口中形成掩模层; 通过部分或完全氧化掩模层形成氧化物掩模; 去除牺牲层; 并使用氧化物掩模作为蚀刻掩模蚀刻下层，以形成下层图案。

公开(公告)号：US07932163B2

公开(公告)日：2011-04-26

申请号：US12029572

申请日：2008-02-12

Applicant: Jong-Heun Lim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Dae-Lok Bae ,  Seong-Kyu Yun ,  Suk-Hun Choi

Inventor： Jong-Heun Lim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Dae-Lok Bae ,  Seong-Kyu Yun ,  Suk-Hun Choi

IPC: H01L21/30 ,  H01L21/46

CPC classification number: H01L27/0688 ,  H01L21/2007 ,  H01L21/8221

Abstract: Spaced apart bonding surfaces are formed on a first substrate. A second substrate is bonded to the bonding surfaces of the first substrate and cleaved to leave respective semiconductor regions from the second substrate on respective ones of the spaced apart bonding surfaces of the first substrate. The bonding surfaces may include surfaces of at least one insulating region on the first substrate, and at least one active device may be formed in and/or on at least one of the semiconductor regions. A device isolation region may be formed adjacent the at least one of the semiconductor regions.

Abstract translation: 间隔开的接合表面形成在第一基底上。 第二衬底被结合到第一衬底的接合表面并且被切割以在第一衬底的相应的间隔的结合表面上的第二衬底上留下相应的半导体区域。 接合表面可以包括第一衬底上的至少一个绝缘区域的表面，并且至少一个有源器件可以形成在半导体区域中的至少一个中和/或至少一个半导体区域中。 器件隔离区域可以形成为与半导体区域中的至少一个相邻。

公开(公告)号：US20100015801A1

公开(公告)日：2010-01-21

申请号：US12460318

申请日：2009-07-16

Applicant: Suk-Hun Choi ,  Chang-Ki Hong ,  Yoon-Ho Son ,  Ju-Young Jung

Inventor： Suk-Hun Choi ,  Chang-Ki Hong ,  Yoon-Ho Son ,  Ju-Young Jung

IPC: H01L21/768

CPC classification number: H01L21/76888 ,  H01L21/76879 ,  H01L21/76883 ,  H01L27/24

Abstract: A plug comprises a first insulating interlayer, a tungsten pattern and a tungsten oxide pattern. The first insulating interlayer has a contact hole formed therethrough on a substrate. The tungsten pattern is formed in the contact hole. The tungsten pattern has a top surface lower than an upper face of the first insulating interlayer. The tungsten oxide pattern is formed in the contact hole and on the tungsten pattern. The tungsten oxide pattern has a level face.

Abstract translation: 插头包括第一绝缘中间层，钨图案和氧化钨图案。 第一绝缘中间层具有在基板上形成的接触孔。 钨图案形成在接触孔中。 钨图案具有比第一绝缘中间层的上表面低的顶表面。 氧化钨图案形成在接触孔和钨图案上。 氧化钨图案具有水平面。

公开(公告)号：US20080200009A1

公开(公告)日：2008-08-21

申请号：US12029572

申请日：2008-02-12

Applicant: Jong-Heun Lim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Dae-Lok Bae ,  Seong-Kyu Yun ,  Suk-Hun Choi

Inventor： Jong-Heun Lim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Dae-Lok Bae ,  Seong-Kyu Yun ,  Suk-Hun Choi

IPC: H01L21/46

CPC classification number: H01L27/0688 ,  H01L21/2007 ,  H01L21/8221

Abstract: Spaced apart bonding surfaces are formed on a first substrate. A second substrate is bonded to the bonding surfaces of the first substrate and cleaved to leave respective semiconductor regions from the second substrate on respective ones of the spaced apart bonding surfaces of the first substrate. The bonding surfaces may include surfaces of at least one insulating region on the first substrate, and at least one active device may be formed in and/or on at least one of the semiconductor regions. A device isolation region may be formed adjacent the at least one of the semiconductor regions.

Abstract translation: 间隔开的接合表面形成在第一基底上。 第二衬底被结合到第一衬底的接合表面并且被切割以在第一衬底的相应的间隔的结合表面上的第二衬底上留下相应的半导体区域。 接合表面可以包括第一衬底上的至少一个绝缘区域的表面，并且至少一个有源器件可以形成在半导体区域中的至少一个中和/或至少一个半导体区域中。 器件隔离区域可以形成为与半导体区域中的至少一个相邻。

公开(公告)号：US20080200007A1

公开(公告)日：2008-08-21

申请号：US12070220

申请日：2008-02-15

Applicant: Jong-Heun Lim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Seong-Kyu Yun ,  Suk-Hun Choi ,  Sang-Yeob Han

Inventor： Jong-Heun Lim ,  Chang-Ki Hong ,  Bo-Un Yoon ,  Seong-Kyu Yun ,  Suk-Hun Choi ,  Sang-Yeob Han

IPC: H01L21/762

CPC classification number: H01L21/76229 ,  H01L21/3212

Abstract: A method of forming a semiconductor device includes: forming a pattern having trenches on a semiconductor substrate; forming a semiconductor layer on the semiconductor device that fills the trenches; planarizing the semiconductor layer using a first planarization process without exposing the pattern; performing an epitaxy growth process on the first planarized semiconductor layer to form a crystalline semiconductor layer; and planarizing the crystalline semiconductor layer until the pattern is exposed to form a crystalline semiconductor pattern.

Abstract translation: 一种形成半导体器件的方法包括：在半导体衬底上形成具有沟槽的图案; 在所述半导体器件上形成填充所述沟槽的半导体层; 使用第一平坦化工艺平坦化半导体层而不暴露图案; 在所述第一平坦化半导体层上进行外延生长工艺以形成晶体半导体层; 并且平坦化晶体半导体层直到图案被曝光以形成晶体半导体图案。