公开(公告)号：US20070250677A1

公开(公告)日：2007-10-25

申请号：US11767863

申请日：2007-06-25

Applicant: Frederick Ware ,  Craig Hampel ,  Wayne Richardson ,  Chad Bellows ,  Lawrence Lai

Inventor： Frederick Ware ,  Craig Hampel ,  Wayne Richardson ,  Chad Bellows ,  Lawrence Lai

IPC: G06F13/372

CPC classification number: G06F3/0659 ,  G06F3/0613 ,  G06F3/0673 ,  G11C7/1006 ,  G11C7/1042 ,  G11C7/22 ,  G11C8/06 ,  G11C11/4076 ,  G11C11/4097

Abstract: A multi-mode memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval is imposed between successive accesses to a given row of the storage cells. Data path circuitry is provided to transfer data between the plurality of storage banks and an external signal path during first and second modes of operation of the memory device. During the first mode of operation a first data item is transferred, in response to a first memory access request, during a first time interval that is not longer than the minimum time interval. During the second mode of operation a plurality of data items are transferred during the first time interval, in response to a plurality of memory access requests.

Abstract translation: 多模式存储器件。 提供了多个存储体，每个存储体包括多行存储单元并且具有访问限制，因为在对存储单元的给定行的连续访问之间至少施加最小访问时间间隔。 提供数据路径电路以在存储器件的第一和第二操作模式期间在多个存储体之间传送数据和外部信号路径。 在第一操作模式期间，响应于第一存储器访问请求，在不长于最小时间间隔的第一时间间隔期间传送第一数据项。 在第二操作模式期间，响应于多个存储器访问请求，在第一时间间隔期间传送多个数据项。

公开(公告)号：US20060039227A1

公开(公告)日：2006-02-23

申请号：US10920508

申请日：2004-08-17

Applicant: Lawrence Lai ,  Wayne Richardson ,  Chad Bellows

Inventor： Lawrence Lai ,  Wayne Richardson ,  Chad Bellows

IPC: G11C7/10

CPC classification number: G11C7/1042 ,  G11C7/22 ,  G11C8/12 ,  G11C2207/2227

Abstract: A memory system includes logical banks divided into sub-banks or collections of sub-banks. The memory system responds to memory-access requests (e.g., read and write) directed to a given logical bank by sequentially accessing sub-banks or collections of sub-banks. Sequential access reduces the impact of power-supply spikes induced by memory operations, and thus facilitates improved system performance. Some embodiments of the memory system combine sequential sub-bank access with other performance-enhancing features, such as wider power buses or increased bypass capacitance, to further enhance performance.

Abstract translation: 记忆系统包括分为子银行或子银行集合的逻辑银行。 存储器系统通过顺序地访问子银行或子银行集合来响应指向给定逻辑银行的存储器访问请求（例如，读取和写入）。 顺序访问减少了由存储器操作引起的电源尖峰的影响，从而有助于提高系统性能。 存储器系统的一些实施例将顺序的子银行访问与诸如更宽的电源总线或增加的旁路电容的其他性能增强特征相结合，以进一步提高性能。

公开(公告)号：US20050248383A1

公开(公告)日：2005-11-10

申请号：US11123225

申请日：2005-05-06

Applicant: Wayne Fang ,  Wayne Richardson ,  Kurt Knorpp

Inventor： Wayne Fang ,  Wayne Richardson ,  Kurt Knorpp

IPC: H03B1/00 ,  H03K3/00 ,  H03K17/693

CPC classification number: H03K17/693

Abstract: A pulse multiplexed output subsystem is disclosed. In one particular exemplary embodiment, the output subsystem may comprise a plurality of pulse generators, a first pair of transistors, and a second pair of transistors, wherein each of the first pair of transistors is coupled to a respective one of a first pair of the plurality of pulse generators, and wherein each of the second pair of transistors is coupled to a respective one of a second pair of the plurality of pulse generators. The output subsystem may also comprise a first pair of resistive loads, wherein each of the first pair of resistive loads is coupled to a respective one of the first pair of transistors and a respective one of the second pair of transistors, and a first current source coupled to the first pair of transistors and the second pair of transistors.

Abstract translation: 公开了脉冲多路复用输出子系统。 在一个特定示例性实施例中，输出子系统可以包括多个脉冲发生器，第一对晶体管和第二对晶体管，其中第一对晶体管中的每一个耦合到第一对晶体管中的相应一个 多个脉冲发生器，并且其中第二对晶体管中的每一个耦合到第二对多个脉冲发生器中的相应一个。 输出子系统还可以包括第一对电阻负载，其中第一对电阻负载中的每一个耦合到第一对晶体管中的相应一个和第二对晶体管中的相应一个，以及第一电流源 耦合到第一对晶体管和第二对晶体管。

公开(公告)号：US08722198B2

公开(公告)日：2014-05-13

申请号：US13446373

申请日：2012-04-13

Applicant: H. Wayne Richardson ,  Robert L. Hodge

Inventor： H. Wayne Richardson ,  Robert L. Hodge

IPC: B32B21/04 ,  C09D5/14 ,  B05D5/00 ,  B05D7/06

CPC classification number: A01N59/20 ,  A01N25/00 ,  A01N25/02 ,  A01N25/04 ,  A01N25/08 ,  A01N25/12 ,  A01N29/10 ,  A01N31/08 ,  A01N31/14 ,  A01N33/00 ,  A01N33/26 ,  A01N43/00 ,  A01N57/00 ,  A01N57/06 ,  A01N57/10 ,  A01N57/14 ,  A01N57/16 ,  A01N59/00 ,  A01N59/16 ,  B27K3/005 ,  B27K3/08 ,  B27K3/22 ,  B27K3/52 ,  C08K3/22 ,  C08K9/02 ,  C09D5/14 ,  C09D5/1618 ,  C09D7/62 ,  C09D7/67 ,  C09D7/68 ,  Y10T428/31989 ,  A01N59/14 ,  A01N25/34 ,  A01N25/26 ,  A01N2300/00

Abstract: The present invention is directed to wood preservative compositions, methods of treating wood, and wood that has been treated with the preservative, which includes injectable particles comprising one or more sparingly soluble copper salts. The copper-based particles are sufficiently insoluble so as to not be easily removed by leaching but are sufficiently soluble to exhibit toxicity to primary organisms primarily responsible for the decay of the wood. Exemplary particles contain for example copper hydroxide, basic copper carbonate, copper carbonate, basic copper sulfates including particularly tribasic copper sulfate, basic copper nitrates, copper oxychlorides, copper borates, basic copper borates, and mixtures thereof. The particles typically have a size distribution in which at least 50% of particles have a diameter smaller than 0.25 μm, 0.2 μm, or 0.15 μm. At least about 20% and even more than 75% of the weight of the particles may be composed of the substantially crystalline copper salt. Wood or a wood product may be impregnated with copper-based particles of the invention.

Abstract translation: 本发明涉及木材防腐剂组合物，已经用防腐剂处理木材和木材的方法，其包括含有一种或多种微溶铜盐的可注射颗粒。 铜基颗粒是足够不溶的，以便通过浸出不容易除去，但足够溶解以对主要负责木材腐烂的原生生物表现出毒性。 示例性颗粒包含例如氢氧化铜，碱式碳酸铜，碳酸铜，碱式硫酸铜，特别是三硫酸铜，碱式硝酸铜，氯氧化铜，铜硼酸盐，碱式硼酸铜及其混合物。 颗粒通常具有尺寸分布，其中至少50％的颗粒具有小于0.25μm，0.2μm或0.15μm的直径。 至少约20％，甚至超过75％的颗粒重量可以由基本上结晶的铜盐组成。 木材或木制品可以用本发明的铜基颗粒浸渍。

公开(公告)号：US07940598B2

公开(公告)日：2011-05-10

申请号：US12177357

申请日：2008-07-22

Applicant: Kishore Kasamsetty ,  Lawrence Lai ,  Wayne Richardson

Inventor： Kishore Kasamsetty ,  Lawrence Lai ,  Wayne Richardson

IPC: G11C8/00

CPC classification number: G11C7/1018 ,  G11C7/1039 ,  G11C7/1048

Abstract: An integrated circuit memory device, system and method embodiments decode interleaved row and column request packets transferred on an interconnect at a first clock frequency. Separate row decode logic and column decode logic, clocked at a relatively slower second clock frequency, output independent column and row control internal signals to a memory core in response to memory commands in the request packets. An integrated circuit memory device includes an interface having separate row and column decode logic circuits for providing independent sets of row and control signals. A row decode logic circuit includes a first row decode logic circuit that provides a first row control signal, such as a row address, and a second row decode logic circuit that provides a second row control signal. A column decode logic circuit includes a first column decode logic circuit that provides a first column control signal, such as a column address and a second column logic circuit that provides a second column control signal.

Abstract translation: 集成电路存储器件，系统和方法实施例以第一时钟频率解码在互连上传送的交错的行和列请求分组。 独立的行解码逻辑和列解码逻辑以相对较慢的第二时钟频率计时，响应于请求数据包中的存储器命令，将独立的列和行控制内部信号输出到存储器内核。 集成电路存储器件包括具有单独的行和列解码逻辑电路的接口，用于提供独立的行和控制信号组。 行解码逻辑电路包括提供诸如行地址的第一行控制信号的第一行解码逻辑电路和提供第二行控制信号的第二行解码逻辑电路。 列解码逻辑电路包括提供诸如列地址的第一列控制信号的第一列解码逻辑电路和提供第二列控制信号的第二列逻辑电路。

公开(公告)号：US20090293761A1

公开(公告)日：2009-12-03

申请号：US11596874

申请日：2005-05-17

Applicant: H. Wayne Richardson ,  Robert L. Hodge ,  Dwight W. Glover ,  Michael P. Pompeo ,  Christopher G. Hayden

Inventor： H. Wayne Richardson ,  Robert L. Hodge ,  Dwight W. Glover ,  Michael P. Pompeo ,  Christopher G. Hayden

IPC: C09D5/14

CPC classification number: A01N59/20 ,  B27K3/005 ,  B27K3/08 ,  B27K3/22 ,  B27K3/52 ,  A01N59/26 ,  A01N59/16 ,  A01N59/14 ,  A01N53/00 ,  A01N51/00 ,  A01N47/38 ,  A01N47/22 ,  A01N47/12 ,  A01N47/02 ,  A01N43/653 ,  A01N43/42 ,  A01N37/34 ,  A01N25/08 ,  A01N25/04 ,  A01N2300/00

Abstract: An aqueous wood-injectable particular-based wood preservative comprising: 1) dispersants in an amount sufficient to maintain biocidal particles in a stable slurry; 2) injectable sub-micron biocidal particles comprising a solid phase of at least one of a sparingly soluble organic biocide, a sparingly soluble copper salt, copper(I)oxide, a sparingly soluble zinc salt, zinc oxide; a sparingly soluble nickel salt; and a sparingly soluble tin salt, wherein less than 2% by weight of the biocidal particles have an average diameter greater than 1 micron, and at least 20% by weight of the biocidal particles have an average diameter greater than 0.08 microns; and 3) at least one pigment particle or dye in an amount sufficient to impart a discernable color or hue to the wood, when compared to wood treated with the same particulate system but without the pigment.

Abstract translation: 一种含木质木材注射剂的特殊木材防腐剂，包括：1）足够量的杀生物剂将分散剂保持在稳定的浆料中; 2）可注射的亚微米杀生物颗粒，其包含微溶有机杀生物剂，微溶铜盐，氧化铜（I），微溶锌盐，氧化锌中的至少一种的固相; 一种微溶的镍盐; 和小溶剂的锡盐，其中小于2重量％的杀生物颗粒的平均直径大于1微米，并且至少20重量％的杀生物颗粒的平均直径大于0.08微米; 和3）至少一种颜料颗粒或染料，其量足以赋予木材可辨别的颜色或色调，与用相同颗粒系统处理但不含颜料的木材相比较。

公开(公告)号：US07461852B2

公开(公告)日：2008-12-09

申请号：US11690465

申请日：2007-03-23

Applicant: Wayne Richardson ,  Kevin Baker

Inventor： Wayne Richardson ,  Kevin Baker

IPC: B60R3/00

CPC classification number: B60R3/00

Abstract: The invention includes a step device for assisting entry into and/or exit from a vehicle such as, for example, high road clearance truck. The step device comprises a generally “W” shaped bar which is separable into said two generally “U” shaped elements for easier packaging, shipping and manipulation of the device. Each of the “U” shaped elements include a cross-bar fixedly attached between, and spanning across, an interior of the generally “U” shaped element. The cross-bars are configured for separately mounting to the vehicle such that the generally “U” shaped elements are independently supported and the generally “U” shaped elements may be adjustable to multiple angles with respect to said vehicle.

Abstract translation: 本发明包括用于辅助进入和/或从车辆例如高清关卡车出口的步进装置。 台阶装置包括通常为“W”形的杆，其可分离成所述两个大致“U”形元件，以便于装置的装运，运输和操纵。 “U”形元件中的每一个包括固定地连接在大致“U”形元件的内部之间并跨越的一个横杆。 横杆被配置为单独地安装到车辆上，使得大致“U”形的元件被独立地支撑，并且大体上“U”形的元件可以相对于所述车辆可调整到多个角度。

公开(公告)号：US20080279032A1

公开(公告)日：2008-11-13

申请号：US12177357

申请日：2008-07-22

Applicant: Kishore Kasamsetty ,  Lawrence Lai ,  Wayne Richardson

Inventor： Kishore Kasamsetty ,  Lawrence Lai ,  Wayne Richardson

IPC: G11C8/10

CPC classification number: G11C7/1018 ,  G11C7/1039 ,  G11C7/1048

Abstract: An integrated circuit memory device, system and method embodiments decode interleaved row and column request packets transferred on an interconnect at a first clock frequency. Separate row decode logic and column decode logic, clocked at a relatively slower second clock frequency, output independent column and row control internal signals to a memory core in response to memory commands in the request packets. An integrated circuit memory device includes an interface having separate row and column decode logic circuits for providing independent sets of row and control signals. A row decode logic circuit includes a first row decode logic circuit that provides a first row control signal, such as a row address, and a second row decode logic circuit that provides a second row control signal. A column decode logic circuit includes a first column decode logic circuit that provides a first column control signal, such as a column address and a second column logic circuit that provides a second column control signal.

Abstract translation: 集成电路存储器件，系统和方法实施例以第一时钟频率解码在互连上传送的交错的行和列请求分组。 独立的行解码逻辑和列解码逻辑以相对较慢的第二时钟频率计时，响应于请求数据包中的存储器命令，将独立的列和行控制内部信号输出到存储器内核。 集成电路存储器件包括具有单独的行和列解码逻辑电路的接口，用于提供独立的行和控制信号组。 行解码逻辑电路包括提供诸如行地址的第一行控制信号的第一行解码逻辑电路和提供第二行控制信号的第二行解码逻辑电路。 列解码逻辑电路包括提供诸如列地址的第一列控制信号的第一列解码逻辑电路和提供第二列控制信号的第二列逻辑电路。

公开(公告)号：US07420874B2

公开(公告)日：2008-09-02

申请号：US11099947

申请日：2005-04-06

Applicant: Kishore Kasamsetty ,  Lawrence Lai ,  Wayne Richardson

Inventor： Kishore Kasamsetty ,  Lawrence Lai ,  Wayne Richardson

IPC: G11C8/18

CPC classification number: G11C7/1018 ,  G11C7/1039 ,  G11C7/1048

Abstract: An integrated circuit memory device, system and method embodiments decode interleaved row and column request packets transferred on an interconnect at a first clock frequency. Separate row decode logic and column decode logic, clocked at a relatively slower second clock frequency, output independent column and row control internal signals to a memory core in response to memory commands in the request packets. An integrated circuit memory device includes an interface having separate row and column decode logic circuits for providing independent sets of row and control signals. A row decode logic circuit includes a first row decode logic circuit that provides a first row control signal, such as a row address, and a second row decode logic circuit that provides a second row control signal. A column decode logic circuit includes a first column decode logic circuit that provides a first column control signal, such as a column address and a second column logic circuit that provides a second column control signal.

Abstract translation: 集成电路存储器件，系统和方法实施例以第一时钟频率解码在互连上传送的交错的行和列请求分组。 独立的行解码逻辑和列解码逻辑以相对较慢的第二时钟频率计时，响应于请求数据包中的存储器命令，将独立的列和行控制内部信号输出到存储器内核。 集成电路存储器件包括具有单独的行和列解码逻辑电路的接口，用于提供独立的行和控制信号组。 行解码逻辑电路包括提供诸如行地址的第一行控制信号的第一行解码逻辑电路和提供第二行控制信号的第二行解码逻辑电路。 列解码逻辑电路包括提供诸如列地址的第一列控制信号的第一列解码逻辑电路和提供第二列控制信号的第二列逻辑电路。

公开(公告)号：USD553101S1

公开(公告)日：2007-10-16

申请号：US29220020

申请日：2004-12-27

Applicant: Wayne Richardson

Designer： Wayne Richardson