公开(公告)号：US20200052063A1

公开(公告)日：2020-02-13

申请号：US16579386

申请日：2019-09-23

Applicant: X-Celeprint Limited

Inventor： Christopher Bower ,  Matthew Meitl ,  Carl Prevatte ,  Ronald S. Cok

IPC: H01L27/32 ,  H01L27/146 ,  H01L27/15

Abstract: A single metal layer device, such as a display or sensor, comprises a substrate and a patterned metal layer. The patterned metal layer forms a two-dimensional array of spatially separated column line segments that each extend only partially across the display substrate in a column direction and forms a one-dimensional array of row lines extending across the display substrate in a row direction different from the column direction. The row lines and column line segments are electrically separate in the patterned metal layer. Spatially separated electrical jumpers are disposed on the display substrate and electrically connect pairs of column line segments adjacent in the column direction. Each electrical jumper has an independent jumper substrate independent of and separate from the display substrate. In certain embodiments, spatially separated light-emitting pixel circuits are disposed on a display substrate and are electrically connected to at least one row line and one column line.

公开(公告)号：US10522710B2

公开(公告)日：2019-12-31

申请号：US16502387

申请日：2019-07-03

Applicant: X-Celeprint Limited

Inventor： Christopher Bower ,  Matthew Meitl ,  David Gomez ,  Carl Prevatte ,  Salvatore Bonafede

IPC: H01L31/0256 ,  H01L33/00 ,  H01L33/32 ,  H01L33/62 ,  H01L33/44 ,  H01L33/36 ,  H01L33/38 ,  H01L29/78 ,  H01L33/26 ,  H01L33/40 ,  H01L21/683 ,  H01L33/20

Abstract: The present invention provides structures and methods that enable the construction of micro-LED chiplets formed on a sapphire substrate that can be micro-transfer printed. Such printed structures enable low-cost, high-performance arrays of electrically connected micro-LEDs useful, for example, in display systems. Furthermore, in an embodiment, the electrical contacts for printed LEDs are electrically interconnected in a single set of process steps. In certain embodiments, formation of the printable micro devices begins while the semiconductor structure remains on a substrate. After partially forming the printable micro devices, a handle substrate is attached to the system opposite the substrate such that the system is secured to the handle substrate. The substrate may then be removed and formation of the semiconductor structures is completed. Upon completion, the printable micro devices may be micro transfer printed to a destination substrate.

公开(公告)号：US10510937B2

公开(公告)日：2019-12-17

申请号：US16186173

申请日：2018-11-09

Applicant: X-Celeprint Limited

Inventor： Matthew Meitl ,  Tanya Yvette Moore ,  Ronald S. Cok ,  Salvatore Bonafede ,  Brook Raymond ,  Christopher Andrew Bower ,  Carl Ray Prevatte, Jr.

IPC: H01L23/538 ,  H01L41/083 ,  H01L23/12 ,  H01L33/62 ,  H01L33/48 ,  H01L41/047 ,  H01L25/065

Abstract: A transfer print structure comprises a destination substrate having a substrate surface and one or more substrate conductors disposed on or in the destination substrate. One or more interconnect structures are disposed on and protrude from the destination substrate in a direction orthogonal to the substrate surface. Each interconnect structure comprises one or more notches, each notch having an opening on an edge of the interconnect structure and extending at least partially through the interconnect structure in a direction parallel to the substrate surface from the edge and a notch conductor disposed at least partially in the notch and electrically connected to one of the substrate conductors. In some embodiments, an electronic component comprising connection posts is transfer printed into electrical contact with a corresponding notch conductor by laterally moving the electronic component over the substrate surface to electrically contact the connection post to the notch conductor.

公开(公告)号：US10475876B2

公开(公告)日：2019-11-12

申请号：US15659500

申请日：2017-07-25

Applicant: X-Celeprint Limited

Inventor： Christopher Bower ,  Matthew Meitl ,  Carl Prevatte ,  Ronald S. Cok

IPC: H01L27/32 ,  H01L27/146 ,  H01L27/15

Abstract: A single metal layer device, such as a display or sensor, comprises a substrate and a patterned metal layer. The patterned metal layer forms a two-dimensional array of spatially separated column line segments that each extend only partially across the display substrate in a column direction and forms a one-dimensional array of row lines extending across the display substrate in a row direction different from the column direction. The row lines and column line segments are electrically separate in the patterned metal layer. Spatially separated electrical jumpers are disposed on the display substrate and electrically connect pairs of column line segments adjacent in the column direction. Each electrical jumper has an independent jumper substrate independent of and separate from the display substrate. In certain embodiments, spatially separated light-emitting pixel circuits are disposed on a display substrate and are electrically connected to at least one row line and one column line.

公开(公告)号：US10475773B2

公开(公告)日：2019-11-12

申请号：US15875955

申请日：2018-01-19

Applicant: OSRAM Opto Semiconductors GmbH ,  X-Celeprint Limited

Inventor： Matthew Meitl ,  Christopher Bower ,  Tansen Varghese

IPC: H01L25/075 ,  H01L33/00 ,  H01L33/50 ,  H01L33/44 ,  H01L21/78 ,  H01L33/56 ,  H01L33/22 ,  H01L33/38 ,  H01L33/60

Abstract: A method for producing a plurality of semiconductor components and a semiconductor component are disclosed. In an embodiment the component includes a light transmissive carrier, a semiconductor body disposed on the light transmissive carrier, the semiconductor body including a first semiconductor layer, a second semiconductor layer and an active region being arranged between the first semiconductor layer and the second semiconductor layer, wherein the semiconductor body includes a first patterned main surface facing the light transmissive carrier and a second main surface facing away from the carrier and a contact structure including a first contact area and a second contact area arranged on the second main surface, wherein the second contact area is electrically connected to the second semiconductor layer, and wherein the contact structure comprises a via extending from the second main surface throughout the second semiconductor layer and the active region into the first semiconductor layer.

公开(公告)号：US10418331B2

公开(公告)日：2019-09-17

申请号：US15863164

申请日：2018-01-05

Applicant: X-Celeprint Limited

Inventor： Christopher Bower

IPC: H01L29/10 ,  H01L23/538 ,  H01L21/683 ,  H01L23/00 ,  H01L21/66

Abstract: An electronic component array includes a backplane substrate, and a plurality of integrated circuit elements on the backplane substrate. Each of the integrated circuit elements includes a chiplet substrate having a connection pad and a conductor element on a surface thereof. The connection pad and the conductor element are electrically separated by an insulating layer that exposes at least a portion of the connection pad. At least one of the integrated circuit elements is misaligned on the backplane substrate relative to a desired position thereon. A plurality of conductive wires are provided on the backplane substrate including the integrated circuit elements thereon, and the connection pad of each of the integrated circuit elements is electrically connected to a respective one of the conductive wires notwithstanding the misalignment of the at least one of the integrated circuit elements. Related fabrication methods are also discussed.

公开(公告)号：US10361677B2

公开(公告)日：2019-07-23

申请号：US15639495

申请日：2017-06-30

Applicant: X-Celeprint Limited

Inventor： Christopher Bower ,  Matthew Meitl ,  Ronald S. Cok ,  Robert R. Rotzoll

IPC: H03H9/56 ,  H03H9/17 ,  H03H9/02 ,  H03H9/05 ,  H03H9/54 ,  H03H9/00 ,  H03H9/58 ,  H03H9/13 ,  H03H9/145 ,  H03H3/02 ,  H03H3/08 ,  H03H9/64

Abstract: A micro-transfer printable transverse bulk acoustic wave filter comprises a piezoelectric filter element having a top side, a bottom side, a left side, and a right side disposed over a sacrificial portion on a source substrate. A top electrode is in contact with the top side and a bottom electrode is in contact with the bottom side. A left acoustic mirror is in contact with the left side and a right acoustic mirror is in contact with the right side. The thickness of the transverse bulk acoustic wave filter is substantially less than its length or width and its length can be greater than its width. The transverse bulk acoustic wave filter can be disposed on, and electrically connected to, a semiconductor substrate comprising an electronic circuit to control the transverse bulk acoustic wave filter and form a composite heterogeneous device that can be micro-transfer printed.

公开(公告)号：US10312405B2

公开(公告)日：2019-06-04

申请号：US15967968

申请日：2018-05-01

Applicant: X-Celeprint Limited

Inventor： Christopher Bower ,  Matthew Meitl

IPC: H01L21/00 ,  H01L23/34 ,  H01L33/00 ,  H01L21/20 ,  H01L21/18 ,  H01L21/78 ,  H01L25/00 ,  H01L23/00 ,  H01L21/683 ,  H01L33/22 ,  H01L33/44

Abstract: The disclosed technology relates generally to a method and system for micro assembling GaN materials and devices to form displays and lighting components that use arrays of small LEDs and high-power, high-voltage, and or high frequency transistors and diodes. GaN materials and devices can be formed from epitaxy on sapphire, silicon carbide, gallium nitride, aluminum nitride, or silicon substrates. The disclosed technology provides systems and methods for preparing GaN materials and devices at least partially formed on several of those native substrates for micro assembly.

公开(公告)号：US10297502B2

公开(公告)日：2019-05-21

申请号：US15445728

申请日：2017-02-28

Applicant: X-Celeprint Limited ,  X-FAB Semiconductor Foundries AG

Inventor： Christopher Andrew Bower ,  Ronald S. Cok ,  William Andrew Nevin ,  Gabriel Kittler

IPC: H01L25/00 ,  H01L21/78 ,  H01L21/762 ,  H01L21/683 ,  H01L21/84

Abstract: A semiconductor structure suitable for micro-transfer printing includes a semiconductor substrate and a patterned insulation layer disposed on or over the semiconductor substrate. The insulation layer pattern forms one or more etch vias in contact with the semiconductor substrate. Each etch via is exposed. A semiconductor device is disposed on the patterned insulation layer and is surrounded by an isolation material in one or more isolation vias that are adjacent to the etch via. The etch via can be at least partially filled with a semiconductor material that is etchable with a common etchant as the semiconductor substrate. Alternatively, the etch via is empty and the semiconductor substrate is patterned to form a gap that separates at least a part of the semiconductor device from the semiconductor substrate and forms a tether physically connecting the semiconductor device to an anchor portion of the semiconductor substrate or the patterned insulation layer.

公开(公告)号：US20190088690A1

公开(公告)日：2019-03-21

申请号：US16192751

申请日：2018-11-15

Applicant: X-Celeprint Limited

Inventor： Christopher Bower ,  Etienne Menard ,  Matthew Meitl ,  Joseph Carr

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/3065 ,  H01L21/3205 ,  H01L29/786 ,  H01L21/768

CPC classification number: H01L27/1266 ,  H01L21/3065 ,  H01L21/32055 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/84 ,  H01L27/1214 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1248 ,  H01L29/78666

Abstract: Methods of forming integrated circuit devices include forming a sacrificial layer on a handling substrate and forming a semiconductor active layer on the sacrificial layer. The semiconductor active layer and the sacrificial layer may be selectively etched in sequence to define an semiconductor-on-insulator (SOI) substrate, which includes a first portion of the semiconductor active layer. A multi-layer electrical interconnect network may be formed on the SOI substrate. This multi-layer electrical interconnect network may be encapsulated by an inorganic capping layer that contacts an upper surface of the first portion of the semiconductor active layer. The capping layer and the first portion of the semiconductor active layer may be selectively etched to thereby expose the sacrificial layer. The sacrificial layer may be selectively removed from between the first portion of the semiconductor active layer and the handling substrate to thereby define a suspended integrated circuit chip encapsulated by the capping layer.