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公开(公告)号:US20190088690A1
公开(公告)日:2019-03-21
申请号:US16192751
申请日:2018-11-15
Applicant: X-Celeprint Limited
Inventor: Christopher Bower , Etienne Menard , Matthew Meitl , Joseph Carr
IPC: H01L27/12 , H01L21/84 , H01L21/3065 , H01L21/3205 , H01L29/786 , H01L21/768
CPC classification number: H01L27/1266 , H01L21/3065 , H01L21/32055 , H01L21/76834 , H01L21/76877 , H01L21/84 , H01L27/1214 , H01L27/1222 , H01L27/124 , H01L27/1248 , H01L29/78666
Abstract: Methods of forming integrated circuit devices include forming a sacrificial layer on a handling substrate and forming a semiconductor active layer on the sacrificial layer. The semiconductor active layer and the sacrificial layer may be selectively etched in sequence to define an semiconductor-on-insulator (SOI) substrate, which includes a first portion of the semiconductor active layer. A multi-layer electrical interconnect network may be formed on the SOI substrate. This multi-layer electrical interconnect network may be encapsulated by an inorganic capping layer that contacts an upper surface of the first portion of the semiconductor active layer. The capping layer and the first portion of the semiconductor active layer may be selectively etched to thereby expose the sacrificial layer. The sacrificial layer may be selectively removed from between the first portion of the semiconductor active layer and the handling substrate to thereby define a suspended integrated circuit chip encapsulated by the capping layer.
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公开(公告)号:US10189243B2
公开(公告)日:2019-01-29
申请号:US15195733
申请日:2016-06-28
Inventor: Etienne Menard , John A. Rogers , Seok Kim , Andrew Carlson
IPC: B41F16/00 , H01L21/683 , H01L23/482 , H01L25/00 , B32B37/00 , B32B41/00 , H01L21/67 , B32B9/00 , B32B37/16 , H01L21/70
Abstract: In a method of printing a transferable component, a stamp including an elastomeric post having three-dimensional relief features protruding from a surface thereof is pressed against a component on a donor substrate with a first pressure that is sufficient to mechanically deform the relief features and a region of the post between the relief features to contact the component over a first contact area. The stamp is retracted from the donor substrate such that the component is adhered to the stamp. The stamp including the component adhered thereto is pressed against a receiving substrate with a second pressure that is less than the first pressure to contact the component over a second contact area that is smaller than the first contact area. The stamp is then retracted from the receiving substrate to delaminate the component from the stamp and print the component onto the receiving substrate. Related apparatus and stamps are also discussed.
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公开(公告)号:US12136620B2
公开(公告)日:2024-11-05
申请号:US17690952
申请日:2022-03-09
Inventor: John A. Rogers , Ralph Nuzzo , Matthew Meitl , Etienne Menard , Alfred Baca , Michael Motala , Jong-Hyun Ahn , Sang-Il Park , Chang-Jae Yu , Heung Cho Ko , Mark Stoykovich , Jongseung Yoon
IPC: H01L25/00 , H01L21/00 , H01L25/04 , H01L25/075 , H01L25/16 , H01L27/12 , H01L27/146 , H01L31/02 , H01L31/0216 , H01L31/0232 , H01L31/0288 , H01L31/0304 , H01L31/043 , H01L31/0525 , H01L31/054 , H01L31/0693 , H01L31/0725 , H01L31/167 , H01L31/18 , H01L33/00 , H01L33/06 , H01L33/30 , H01L33/48 , H01L33/52 , H01L33/54 , H01L33/56 , H01L33/58 , H01L33/62 , H01S5/02 , H01S5/02251 , H01S5/183 , H01S5/30 , H01S5/343 , H01S5/42 , B82Y10/00 , H01L29/786
Abstract: Provided are optical devices and systems fabricated, at least in part, via printing-based assembly and integration of device components. In specific embodiments the present invention provides light emitting systems, light collecting systems, light sensing systems and photovoltaic systems comprising printable semiconductor elements, including large area, high performance macroelectronic devices. Optical systems of the present invention comprise semiconductor elements assembled, organized and/or integrated with other device components via printing techniques that exhibit performance characteristics and functionality comparable to single crystalline semiconductor based devices fabricated using conventional high temperature processing methods. Optical systems of the present invention have device geometries and configurations, such as form factors, component densities, and component positions, accessed by printing that provide a range of useful device functionalities. Optical systems of the present invention include devices and device arrays exhibiting a range of useful physical and mechanical properties including flexibility, shapeability, conformability and stretchablity.
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公开(公告)号:US10522575B2
公开(公告)日:2019-12-31
申请号:US16192751
申请日:2018-11-15
Applicant: X-Celeprint Limited
Inventor: Christopher Bower , Etienne Menard , Matthew Meitl , Joseph Carr
IPC: H01L29/10 , H01L27/12 , H01L21/84 , H01L21/3065 , H01L21/3205 , H01L21/768 , H01L29/786
Abstract: Methods of forming integrated circuit devices include forming a sacrificial layer on a handling substrate and forming a semiconductor active layer on the sacrificial layer. The semiconductor active layer and the sacrificial layer may be selectively etched in sequence to define an semiconductor-on-insulator (SOI) substrate, which includes a first portion of the semiconductor active layer. A multi-layer electrical interconnect network may be formed on the SOI substrate. This multi-layer electrical interconnect network may be encapsulated by an inorganic capping layer that contacts an upper surface of the first portion of the semiconductor active layer. The capping layer and the first portion of the semiconductor active layer may be selectively etched to thereby expose the sacrificial layer. The sacrificial layer may be selectively removed from between the first portion of the semiconductor active layer and the handling substrate to thereby define a suspended integrated circuit chip encapsulated by the capping layer.
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公开(公告)号:US11309305B2
公开(公告)日:2022-04-19
申请号:US16667215
申请日:2019-10-29
Inventor: John A. Rogers , Ralph Nuzzo , Matthew Meitl , Etienne Menard , Alfred Baca , Michael Motala , Jong-Hyun Ahn , Sang-Il Park , Chang-Jae Yu , Heung Cho Ko , Mark Stoykovich , Jongseung Yoon
IPC: H01L25/00 , H01L27/12 , H01L21/00 , H01L31/0725 , H01L31/18 , H01S5/42 , H01L25/075 , H01L31/054 , H01L33/58 , H01L33/00 , H01S5/02251 , H01L31/0525 , H01L25/16 , H01L33/54 , H01L33/56 , H01L25/04 , H01L31/043 , H01L31/0216 , H01L31/0232 , H01L31/0288 , H01L31/0693 , H01L31/167 , H01L33/06 , H01L33/30 , H01L33/48 , H01L33/62 , H01S5/02 , H01S5/343 , H01L27/146 , H01L31/02 , H01L31/0304 , H01L33/52 , H01S5/183 , H01S5/30 , B82Y10/00 , H01L29/786
Abstract: Provided are optical devices and systems fabricated, at least in part, via printing-based assembly and integration of device components. In specific embodiments the present invention provides light emitting systems, light collecting systems, light sensing systems and photovoltaic systems comprising printable semiconductor elements, including large area, high performance macroelectronic devices. Optical systems of the present invention comprise semiconductor elements assembled, organized and/or integrated with other device components via printing techniques that exhibit performance characteristics and functionality comparable to single crystalline semiconductor based devices fabricated using conventional high temperature processing methods. Optical systems of the present invention have device geometries and configurations, such as form factors, component densities, and component positions, accessed by printing that provide a range of useful device functionalities. Optical systems of the present invention include devices and device arrays exhibiting a range of useful physical and mechanical properties including flexibility, shapeability, conformability and stretchablity.
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公开(公告)号:US20200098796A1
公开(公告)日:2020-03-26
申请号:US16697104
申请日:2019-11-26
Applicant: X-Celeprint Limited
Inventor: Christopher Bower , Etienne Menard , Matthew Meitl , Joseph Carr
IPC: H01L27/12 , H01L21/84 , H01L21/3065 , H01L21/3205 , H01L21/768 , H01L29/786
Abstract: Methods of forming integrated circuit devices include forming a sacrificial layer on a handling substrate and forming a semiconductor active layer on the sacrificial layer. The semiconductor active layer and the sacrificial layer may be selectively etched in sequence to define an semiconductor-on-insulator (SOI) substrate, which includes a first portion of the semiconductor active layer. A multi-layer electrical interconnect network may be formed on the SOI substrate. This multi-layer electrical interconnect network may be encapsulated by an inorganic capping layer that contacts an upper surface of the first portion of the semiconductor active layer. The capping layer and the first portion of the semiconductor active layer may be selectively etched to thereby expose the sacrificial layer. The sacrificial layer may be selectively removed from between the first portion of the semiconductor active layer and the handling substrate to thereby define a suspended integrated circuit chip encapsulated by the capping layer.
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公开(公告)号:US10181483B2
公开(公告)日:2019-01-15
申请号:US14879581
申请日:2015-10-09
Inventor: Etienne Menard , Matthew Meitl , John A. Rogers
IPC: H01L27/00 , H01L27/12 , H01L21/683 , H01L21/768 , H01L23/48 , H01L27/146 , H01L31/0203 , H01L31/048 , H05K1/18 , H05K13/04 , H01L23/544 , H01L31/18 , H01L31/043 , H01L21/78 , H01L23/00 , H01S5/022
Abstract: A method of printing transferable components includes pressing a stamp including at least one transferable semiconductor component thereon on a target substrate such that the at least one transferable component and a surface of the target substrate contact opposite surfaces of a conductive eutectic layer. During pressing of the stamp on the target substrate, the at least one transferable component is exposed to electromagnetic radiation that is directed through the transfer stamp to reflow the eutectic layer. The stamp is then separated from the target substrate to delaminate the at least one transferable component from the stamp and print the at least one transferable component onto the surface of the target substrate. Related systems and methods are also discussed.
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公开(公告)号:US10163945B2
公开(公告)日:2018-12-25
申请号:US15864813
申请日:2018-01-08
Applicant: X-Celeprint Limited
Inventor: Christopher Bower , Etienne Menard , Matthew Meitl , Joseph Carr
IPC: H01L21/311 , H01L27/12 , H01L21/84 , H01L21/3065 , H01L21/3205 , H01L21/768 , H01L29/786
Abstract: Methods of forming integrated circuit devices include forming a sacrificial layer on a handling substrate and forming a semiconductor active layer on the sacrificial layer. The semiconductor active layer and the sacrificial layer may be selectively etched in sequence to define an semiconductor-on-insulator (SOI) substrate, which includes a first portion of the semiconductor active layer. A multi-layer electrical interconnect network may be formed on the SOI substrate. This multi-layer electrical interconnect network may be encapsulated by an inorganic capping layer that contacts an upper surface of the first portion of the semiconductor active layer. The capping layer and the first portion of the semiconductor active layer may be selectively etched to thereby expose the sacrificial layer. The sacrificial layer may be selectively removed from between the first portion of the semiconductor active layer and the handling substrate to thereby define a suspended integrated circuit chip encapsulated by the capping layer.
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公开(公告)号:US20180130829A1
公开(公告)日:2018-05-10
申请号:US15864813
申请日:2018-01-08
Applicant: X-Celeprint Limited
Inventor: Christopher Bower , Etienne Menard , Matthew Meitl , Joseph Carr
IPC: H01L27/12 , H01L29/786
CPC classification number: H01L27/1266 , H01L21/3065 , H01L21/32055 , H01L21/76834 , H01L21/76877 , H01L21/84 , H01L27/1214 , H01L27/1222 , H01L27/124 , H01L27/1248 , H01L29/78666
Abstract: Methods of forming integrated circuit devices include forming a sacrificial layer on a handling substrate and forming a semiconductor active layer on the sacrificial layer. The semiconductor active layer and the sacrificial layer may be selectively etched in sequence to define an semiconductor-on-insulator (SOI) substrate, which includes a first portion of the semiconductor active layer. A multi-layer electrical interconnect network may be formed on the SOI substrate. This multi-layer electrical interconnect network may be encapsulated by an inorganic capping layer that contacts an upper surface of the first portion of the semiconductor active layer. The capping layer and the first portion of the semiconductor active layer may be selectively etched to thereby expose the sacrificial layer. The sacrificial layer may be selectively removed from between the first portion of the semiconductor active layer and the handling substrate to thereby define a suspended integrated circuit chip encapsulated by the capping layer.
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公开(公告)号:US09923133B2
公开(公告)日:2018-03-20
申请号:US14831236
申请日:2015-08-20
Applicant: X-Celeprint Limited
Inventor: Christopher Bower , Etienne Menard , Matthew Meitl
IPC: H01L23/58 , H01L33/62 , H01L21/683 , H01L21/66 , G01R31/26 , H01L21/308 , H01L25/075 , H01L33/16 , H01L33/30 , H01L33/34 , H01L33/48
CPC classification number: H01L33/62 , G01R31/26 , G01R31/2644 , H01L21/308 , H01L21/6835 , H01L22/14 , H01L22/30 , H01L22/32 , H01L25/0753 , H01L33/16 , H01L33/30 , H01L33/34 , H01L33/48 , H01L2221/6835 , H01L2221/68381 , H01L2924/0002 , H01L2924/00
Abstract: A substrate includes an anchor area physically secured to a surface of the substrate and at least one printable electronic component. The at least one printable electronic component includes an active layer having one or more active elements thereon, and is suspended over the surface of the substrate by electrically conductive breakable tethers. The electrically conductive breakable tethers include an insulating layer and a conductive layer thereon that physically secure and electrically connect the at least one printable electronic component to the anchor area, and are configured to be preferentially fractured responsive to pressure applied thereto. Related methods of fabrication and testing are also discussed.
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