Abstract:
A new jacket design method is disclosed, especially for deepwater water heavy jacket applications. The method utilizes a special type of air bags, called Ship Launching Air Bags (SLAB), to provide low cost temporary buoyancy used for jacket installation purpose only. A designer only needs to satisfy the jacket stiffness for the resistance of environmental and gravity loads without the consideration of jacket reserve buoyancy. The required jacket reserve buoyancy could be increased with the utilization of temporally attached SLABs during the jacket installation.
Abstract:
The invention provides a surface mount technology process for an advanced quad flat no-lead package process and a stencil used therewith. The surface mount technology process for an advanced quad flat no-lead package includes providing a printed circuit board. A stencil with first openings is mounted over the printed circuit board. A solder paste is printed passing the first openings to form first solder paste patterns. The stencil is taken off. A component placement process is performed to place the advanced quad flat no-lead package comprising a die pad on the printed circuit board, wherein the first solder paste patterns contact a lower surface of the die pad, and an area ratio of the first openings to the lower surface of the die pad is between 1:2 and 1:10. A reflow process is performed to melt the first solder paste patterns to surround a sidewall of the die pad.
Abstract:
A pilot-measurement control method and a dual-mode terminal are provided. After entering a tunnel state, an idle state protocol submodule does not wait for a measurement start command to trigger pilot measurement, but instead, directly triggers pilot measurement by actively searching for high rate packet data (HRPD) measurement permission variable information. Alternatively, measurement indication information sent by an initialization protocol submodule is buffered in advance, so that after entering the tunnel state, the idle state protocol submodule can trigger pilot measurement by searching for the buffered information. Alternatively, the idle state protocol submodule performs pilot measurement according to received measurement indication information sent by an air interface connection management protocol submodule when the idle state protocol submodule is activated.
Abstract:
The present invention provides a method and a compiler of compiling a source program. According to an aspect of the present invention, there is provided a method of compiling a source program comprising: identifying a hint related to vector aligning when syntax analyzing said source program; and generating a simplified code based on said identified hint related to vector aligning when generating a code.
Abstract:
A pre-solder method for a multi-row quad flat no-lead (QFN) packaged chip is provided. Solder paste is applied on at least one pad of the multi-row QFN packaged chip. The multi-row QFN packaged chip is heated, such that the solder paste on the at least one pad of the multi-row QFN packaged chip becomes solid solder before the multi-row QFN packaged chip is mounted on a substrate.
Abstract:
A two-dimensional (2D) mesh is applied over a distortion surface to approximate a lens roll-off distortion pattern. The process to apply the 2D mesh distributes a plurality of grid points among the distortion pattern and sub-samples the distortion pattern to derive corrected digital gains at each grid location. Non-grid pixels underlying grid blocks having a grid point at each corner are adjusted based on the approximation of the lens roll-off for the grid points of the grid block. In one example, bilinear interpolation is used. The techniques universally correct lens roll-off distortion irregardless of the distortion pattern shape or type. The technique may also correct for green channel imbalance.
Abstract:
An interleaving control type inverter includes a waveform generator to generate a predetermined waveform; a plurality of first signal generators to receive the predetermined waveform and a phase voltage to generate a first control signal and a second control signal corresponding to the phases of the phase voltage; a second signal generator to receive the predetermined waveform and generate a first interleaving signal and a second interleaving signal; a plurality of first multiplexers to receive the first interleaving signal and process the first control signal to become a plurality of first control signals; a plurality of second multiplexers to receive the second interleaving signal and process the second control signal to become a plurality of second control signals; and a plurality of power transistors that switch according to the first control signals and the second control signals.
Abstract:
An interleaving control type inverter includes a waveform generator to generate a predetermined waveform; a plurality of first signal generators to receive the predetermined waveform and a phase voltage to generate a first control signal and a second control signal corresponding to the phases of the phase voltage; a second signal generator to receive the predetermined waveform and generate a first interleaving signal and a second interleaving signal; a plurality of first multiplexers to receive the first interleaving signal and process the first control signal to become a plurality of first control signals; a plurality of second multiplexers to receive the second interleaving signal and process the second control signal to become a plurality of second control signals; and a plurality of power transistors that switch according to the first control signals and the second control signals.
Abstract:
Generally stated a method and an accompanying apparatus provides for a voice recognition system (300) with programmable front end processing unit (400). The front end processing unit (400) requests and receives different configuration files at different times for processing voice data in the voice recognition system (300). The configuration files are communicated to the front end unit via a communication link (310) for configuring the front end processing unit (400). A microprocessor may provide the front end configuration files on the communication link at different times.