公开(公告)号：US08755019B2

公开(公告)日：2014-06-17

申请号：US13193488

申请日：2011-07-28

Applicant: Ji-Young Park ,  Sang Gab Kim ,  Yong-Mo Choi ,  Hyung Jun Kim ,  Sung-Haeng Cho ,  Hong-Sick Park ,  Byeong-Jin Lee ,  Soo-Wan Yoon

Inventor： Ji-Young Park ,  Sang Gab Kim ,  Yong-Mo Choi ,  Hyung Jun Kim ,  Sung-Haeng Cho ,  Hong-Sick Park ,  Byeong-Jin Lee ,  Soo-Wan Yoon

IPC: G02F1/1339 ,  G02F1/13

CPC classification number: H01L27/1288 ,  G02F1/1362 ,  G02F2001/136231 ,  H01L29/41733

Abstract: A method of manufacturing a liquid crystal display includes: forming a gate line including a gate electrode on a first substrate; forming a gate insulating layer on the gate line; sequentially forming a semiconductor layer, an amorphous silicon layer, and a data metal layer on the entire surface of the gate insulating layer; aligning the edges of the semiconductor layer and the data metal layer; forming a transparent conductive layer on the gate insulating layer and the data metal layer; forming a first pixel electrode and a second pixel electrode by patterning the transparent conductive layer; and forming a data line including a source electrode, a drain electrode, and an ohmic contact layer by etching the data metal layer and the amorphous silicon layer, using the first pixel electrode and the second pixel electrode as a mask, and exposing the semiconductor between the source electrode and the drain electrode.

Abstract translation: 制造液晶显示器的方法包括：在第一基板上形成包括栅电极的栅极线; 在栅极线上形成栅极绝缘层; 在栅极绝缘层的整个表面上依次形成半导体层，非晶硅层和数据金属层; 对准半导体层和数据金属层的边缘; 在栅绝缘层和数据金属层上形成透明导电层; 通过图案化透明导电层形成第一像素电极和第二像素电极; 以及使用所述第一像素电极和所述第二像素电极作为掩模，通过蚀刻所述数据金属层和所述非晶硅层来形成包括源电极，漏电极和欧姆接触层的数据线，并且使所述半导体在 源电极和漏电极。

公开(公告)号：US08450129B2

公开(公告)日：2013-05-28

申请号：US13231225

申请日：2011-09-13

Applicant: Hong-Kee Chin ,  Sang-Gab Kim ,  Woong-Kwon Kim ,  Yong-Mo Choi ,  Seung-Ha Choi ,  Shin-Il Choi ,  Ho-Jun Lee ,  Jung-Suk Bang ,  Yu-Gwang Jeong

Inventor： Hong-Kee Chin ,  Sang-Gab Kim ,  Woong-Kwon Kim ,  Yong-Mo Choi ,  Seung-Ha Choi ,  Shin-Il Choi ,  Ho-Jun Lee ,  Jung-Suk Bang ,  Yu-Gwang Jeong

IPC: H01L33/16

CPC classification number: H01L27/12 ,  H01L27/1248 ,  H01L27/1288

Abstract: A thin film transistor (TFT) substrate is provided in which a sufficiently large contact area between conductive materials is provided in a contact portion and a method of fabricating the TFT substrate. The TFT substrate includes a gate interconnection line formed on an insulating substrate, a gate insulating layer covering the gate interconnection line, a semiconductor layer arranged on the gate insulating layer, a data interconnection line including a data line, a source electrode and a drain electrode formed on the semiconductor layer, a first passivation layer formed on the data interconnection line and exposing the drain electrode, a second passivation layer formed on the first passivation film and a pixel electrode electrically connected to the drain electrode. An outer sidewall of the second passivation layer is positioned inside an outer sidewall of the first passivation layer.

Abstract translation: 提供一种薄膜晶体管（TFT）基板，其中在接触部分中提供导电材料之间的足够大的接触面积以及制造TFT基板的方法。 TFT基板包括形成在绝缘基板上的栅极互连线，覆盖栅极互连线的栅极绝缘层，布置在栅极绝缘层上的半导体层，包括数据线，源极和漏极的数据互连线 形成在所述半导体层上，形成在所述数据互连线上并暴露所述漏电极的第一钝化层，形成在所述第一钝化膜上的第二钝化层和与所述漏电极电连接的像素电极。 第二钝化层的外侧壁位于第一钝化层的外侧壁的内侧。

公开(公告)号：US08409916B2

公开(公告)日：2013-04-02

申请号：US13233399

申请日：2011-09-15

Applicant: Kap-Soo Yoon ,  Sung-Hoon Yang ,  Byoung-June Kim ,  Czang-Ho Lee ,  Sung-Ryul Kim ,  Hwa-Yeul Oh ,  Jae-Ho Choi ,  Yong-Mo Choi

Inventor： Kap-Soo Yoon ,  Sung-Hoon Yang ,  Byoung-June Kim ,  Czang-Ho Lee ,  Sung-Ryul Kim ,  Hwa-Yeul Oh ,  Jae-Ho Choi ,  Yong-Mo Choi

IPC: H01L21/00 ,  H01L21/16

CPC classification number: H01L29/7869 ,  H01L27/1225

Abstract: A thin film transistor substrate includes an insulating plate; a gate electrode disposed on the insulating plate; a semiconductor layer comprising a metal oxide, wherein the metal oxide has oxygen defects of less than or equal to 3%, and wherein the metal oxide comprises about 0.01 mole/cm3 to about 0.3 mole/cm3 of a 3d transition metal; a gate insulating layer disposed between the gate electrode and the semiconductor layer; and a source electrode and a drain electrode disposed on the semiconductor layer. Also described is a display substrate. The metal oxide has oxygen defects of less than or equal to 3%, and is doped with about 0.01 mole/cm3 to about 0.3 mole/cm3 of 3d transition metal. The metal oxide comprises indium oxide or titanium oxide. The 3d transition metal includes at least one 3d transition metal selected from the group consisting of chromium, cobalt, nickel, iron, manganese, and mixtures thereof.

Abstract translation: 薄膜晶体管基板包括绝缘板; 设置在绝缘板上的栅电极; 包含金属氧化物的半导体层，其中所述金属氧化物具有小于或等于3％的氧缺陷，并且其中所述金属氧化物包含约0.01mol / cm 3至约0.3mol / cm 3的3d过渡金属; 设置在所述栅极电极和所述半导体层之间的栅极绝缘层; 以及设置在半导体层上的源电极和漏电极。 还描述了显示基板。 金属氧化物具有小于或等于3％的氧缺陷，并且掺杂有约0.01摩尔/ cm3至约0.3摩尔/ cm3的3d过渡金属。 金属氧化物包括氧化铟或二氧化钛。 3d过渡金属包括选自铬，钴，镍，铁，锰及其混合物中的至少一种3d过渡金属。

公开(公告)号：US08189131B2

公开(公告)日：2012-05-29

申请号：US12188956

申请日：2008-08-08

Applicant: Kap-Soo Yoon ,  Sung-Hoon Yang ,  Sung-Ryul Kim ,  Hwa-Yeul Oh ,  Jae-Ho Choi ,  Yong-Mo Choi

Inventor： Kap-Soo Yoon ,  Sung-Hoon Yang ,  Sung-Ryul Kim ,  Hwa-Yeul Oh ,  Jae-Ho Choi ,  Yong-Mo Choi

IPC: G02F1/136

CPC classification number: H01L29/78696 ,  B82Y10/00 ,  H01L29/778 ,  H01L29/78687

Abstract: A thin-film transistor (TFT) includes a gate electrode, a semiconductor pattern, a source electrode, and a drain electrode. The semiconductor pattern includes an active layer being overlapped with the gate electrode and a low band gap portion having a lower energy band gap than the active layer. The source and drain electrodes are spaced apart from each other to be overlapped with the semiconductor pattern. Therefore, the semiconductor pattern includes a low band gap portion having a lower energy band gap than the active layer, so that electron mobility may be increased in a channel formed along the low band gap portion so that electric characteristics of the TFT may be enhanced.

Abstract translation: 薄膜晶体管（TFT）包括栅电极，半导体图案，源电极和漏电极。 半导体图案包括与栅电极重叠的有源层和具有比有源层更低的能带隙的低带隙部分。 源极和漏极彼此间隔开以与半导体图案重叠。 因此，半导体图案包括具有比有源层低的能带隙的低带隙部分，使得沿着低带隙部分形成的沟道中的电子迁移率可能增加，从而可以提高TFT的电特性。

公开(公告)号：US20100148182A1

公开(公告)日：2010-06-17

申请号：US12429388

申请日：2009-04-24

Applicant: Hong-Kee CHIN ,  Sang-Gab KIM ,  Woong-Kwon KIM ,  Yong-Mo CHOI ,  Seung-Ha CHOI ,  Shin-Il CHOI ,  Ho-Jun LEE ,  Jung-Suk BANG ,  Yu-Gwang JEONG

Inventor： Hong-Kee CHIN ,  Sang-Gab KIM ,  Woong-Kwon KIM ,  Yong-Mo CHOI ,  Seung-Ha CHOI ,  Shin-Il CHOI ,  Ho-Jun LEE ,  Jung-Suk BANG ,  Yu-Gwang JEONG

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L27/12 ,  H01L27/1248 ,  H01L27/1288

Abstract: A thin film transistor (TFT) substrate is provided in which a sufficiently large contact area between conductive materials is provided in a contact portion and a method of fabricating the TFT substrate. The TFT substrate includes a gate interconnection line formed on an insulating substrate, a gate insulating layer covering the gate interconnection line, a semiconductor layer arranged on the gate insulating layer, a data interconnection line including a data line, a source electrode and a drain electrode formed on the semiconductor layer, a first passivation layer formed on the data interconnection line and exposing the drain electrode, a second passivation layer formed on the first passivation film and a pixel electrode electrically connected to the drain electrode. An outer sidewall of the second passivation layer is positioned inside an outer sidewall of the first passivation layer.

Abstract translation: 提供一种薄膜晶体管（TFT）基板，其中在接触部分中提供导电材料之间的足够大的接触面积以及制造TFT基板的方法。 TFT基板包括形成在绝缘基板上的栅极互连线，覆盖栅极互连线的栅极绝缘层，布置在栅极绝缘层上的半导体层，包括数据线，源极和漏极的数据互连线 形成在所述半导体层上，形成在所述数据互连线上并暴露所述漏电极的第一钝化层，形成在所述第一钝化膜上的第二钝化层和与所述漏电极电连接的像素电极。 第二钝化层的外侧壁位于第一钝化层的外侧壁的内侧。

公开(公告)号：US20090185126A1

公开(公告)日：2009-07-23

申请号：US12332249

申请日：2008-12-10

Applicant: Sung Ryul Kim ,  Yong-Mo Choi ,  Sung-Hoon Yang ,  Hwa-Yeul Oh ,  Kap-Soo Yoon ,  Jae-Ho Choi ,  Seong-Hun Kim

Inventor： Sung Ryul Kim ,  Yong-Mo Choi ,  Sung-Hoon Yang ,  Hwa-Yeul Oh ,  Kap-Soo Yoon ,  Jae-Ho Choi ,  Seong-Hun Kim

IPC: G02F1/1343 ,  B32B15/04 ,  B32B7/02 ,  H05H1/24 ,  H05K1/09

CPC classification number: G02F1/136286 ,  G02F2001/13629 ,  G02F2001/136295 ,  Y10T428/24975

Abstract: Provided are a metal line, a method of forming the same, and a display using the same. To increase resistance of a metal line having a multilayered structure of CuO/Cu and prevent blister formation, a plasma treatment is performed using a nitrogen-containing gas and a silicon-containing gas or using a hydrogen or argon as and the silicon-containing gas. Accordingly, a plasma treatment layer such as a SiNx or Si layer is thinly formed on the copper layer, thereby preventing an increase in resistance of the copper layer and also preventing blister formation caused by the damage of a copper oxide layer. Consequently, it is possible to improve the reliability of a copper line and thus enhance the reliability of a device.

Abstract translation: 提供一种金属线，其形成方法和使用该线的显示器。 为了增加具有CuO / Cu多层结构的金属线的电阻并防止起泡形成，使用含氮气体和含硅气体或使用氢或氩作为含硅气体进行等离子体处理 。 因此，在铜层上薄膜地形成诸如SiN x或Si层的等离子体处理层，从而防止铜层的电阻增加，并且还防止由氧化铜层损坏引起的起泡形成。 因此，可以提高铜线的可靠性，从而提高装置的可靠性。

公开(公告)号：US20090180045A1

公开(公告)日：2009-07-16

申请号：US12353152

申请日：2009-01-13

Applicant: Kap-Soo Yoon ,  Sung-Hoon Yang ,  Sung-Ryul Kim ,  Hwa-Yeul Oh ,  Jae-Ho Choi ,  Yong-Mo Choi

Inventor： Kap-Soo Yoon ,  Sung-Hoon Yang ,  Sung-Ryul Kim ,  Hwa-Yeul Oh ,  Jae-Ho Choi ,  Yong-Mo Choi

IPC: G02F1/1368 ,  H01L27/08 ,  H01L29/02

CPC classification number: G02F1/1368 ,  G02F2202/108 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/7869

Abstract: Provided are a display substrate and a display device including the same. The display substrate includes: gate wiring; a first semiconductor pattern formed on the gate wiring and having a first energy bandgap; a second semiconductor pattern formed on the first semiconductor pattern and having a second energy bandgap which is greater than the first energy bandgap; data wiring formed on the first semiconductor pattern; and a pixel electrode electrically connected to the data wiring. Because the second energy bandgap is larger than the first energy bandgap, a quantum well is formed in the first semiconductor pattern, enhancing electron mobility therein.

Abstract translation: 提供了一种显示基板和包括该基板的显示装置。 显示基板包括：栅极布线; 形成在所述栅极布线上并具有第一能量带隙的第一半导体图案; 形成在所述第一半导体图案上并具有大于所述第一能带隙的第二能带隙的第二半导体图案; 形成在第一半导体图案上的数据布线; 以及与数据配线电连接的像素电极。 由于第二能量带隙大于第一能带隙，所以在第一半导体图案中形成量子阱，增强其中的电子迁移率。

公开(公告)号：US20090167974A1

公开(公告)日：2009-07-02

申请号：US12261470

申请日：2008-10-30

Applicant: Jae-ho CHOI ,  Sung-hoon YANG ,  Kap-soo YOON ,  Sung-ryul KIM ,  Hwa-yeul OH ,  Yong-mo CHOI

Inventor： Jae-ho CHOI ,  Sung-hoon YANG ,  Kap-soo YOON ,  Sung-ryul KIM ,  Hwa-yeul OH ,  Yong-mo CHOI

IPC: G02F1/136 ,  H01L29/22 ,  H01L21/34

CPC classification number: H01L29/7869 ,  H01L21/02554 ,  H01L21/02565 ,  H01L27/1225

Abstract: A display substrate, a display device including the display substrate, and a method of fabricating the display substrate are provided. The display substrate includes a gate electrode; a gate-insulating layer disposed on the gate electrode; an oxide semiconductor pattern disposed on the gate-insulating layer; a source electrode disposed on the oxide semiconductor pattern; and a drain electrode disposed on the oxide semiconductor pattern and separated from the source electrode, wherein at least one portion of at least one of the gate-insulating layer or the oxide semiconductor pattern is plasma-processed.

Abstract translation: 提供了显示基板，包括显示基板的显示装置和制造显示基板的方法。 显示基板包括栅电极; 设置在所述栅电极上的栅极绝缘层; 设置在所述栅极绝缘层上的氧化物半导体图案; 设置在所述氧化物半导体图案上的源电极; 以及设置在所述氧化物半导体图案上并与所述源电极分离的漏电极，其中所述栅极绝缘层或所述氧化物半导体图案中的至少一个的至少一部分被等离子体处理。

公开(公告)号：US20080258143A1

公开(公告)日：2008-10-23

申请号：US12100436

申请日：2008-04-10

Applicant: Sung-Ryul KIM ,  Sung-Hoon YANG ,  Byoung-June KIM ,  Czang-Ho LEE ,  Jae-Ho CHOI ,  Hwa-Yeul OH ,  Yong-Mo CHOI

Inventor： Sung-Ryul KIM ,  Sung-Hoon YANG ,  Byoung-June KIM ,  Czang-Ho LEE ,  Jae-Ho CHOI ,  Hwa-Yeul OH ,  Yong-Mo CHOI

IPC: H01L29/786 ,  H01L21/36

CPC classification number: H01L29/78618 ,  H01L29/458 ,  H01L29/66765 ,  H01L29/7869

Abstract: A method of manufacturing a thin film transistor (“TFT”) substrate includes forming a first conductive pattern group including a gate electrode on a substrate, forming a gate insulating layer on the first conductive pattern group, forming a semiconductor layer and an ohmic contact layer on the gate insulating layer by patterning an amorphous silicon layer and an oxide semiconductor layer, forming a second conductive pattern group including a source electrode and a drain electrode on the ohmic contact layer by patterning a data metal layer, forming a protection layer including a contact hole on the second conductive pattern group, and forming a pixel electrode on the contact hole of the protection layer. The TFT substrate including the ohmic contact layer formed of an oxide semiconductor is further provided.

Abstract translation: 制造薄膜晶体管（“TFT”）基板的方法包括在基板上形成包括栅电极的第一导电图案组，在第一导电图案组上形成栅极绝缘层，形成半导体层和欧姆接触层 通过图案化非晶硅层和氧化物半导体层，在栅极绝缘层上，通过图案化数据金属层，在欧姆接触层上形成包括源电极和漏电极的第二导电图案组，形成包括接触的保护层 并且在保护层的接触孔上形成像素电极。 还提供了包括由氧化物半导体形成的欧姆接触层的TFT基板。

公开(公告)号：US20120003769A1

公开(公告)日：2012-01-05

申请号：US13233399

申请日：2011-09-15

Applicant: Kap-Soo YOON ,  Sung-Hoon YANG ,  Byoung-June KIM ,  Czang-Ho LEE ,  Sung-Ryul KIM ,  Hwa-Yeul OH ,  Jae-Ho CHOI ,  Yong-Mo CHOI

Inventor： Kap-Soo YOON ,  Sung-Hoon YANG ,  Byoung-June KIM ,  Czang-Ho LEE ,  Sung-Ryul KIM ,  Hwa-Yeul OH ,  Jae-Ho CHOI ,  Yong-Mo CHOI

IPC: H01L33/08

CPC classification number: H01L29/7869 ,  H01L27/1225

Abstract: A thin film transistor substrate includes an insulating plate; a gate electrode disposed on the insulating plate; a semiconductor layer comprising a metal oxide, wherein the metal oxide has oxygen defects of less than or equal to 3%, and wherein the metal oxide comprises about 0.01 mole/cm3 to about 0.3 mole/cm3 of a 3d transition metal; a gate insulating layer disposed between the gate electrode and the semiconductor layer; and a source electrode and a drain electrode disposed on the semiconductor layer. Also described is a display substrate. The metal oxide has oxygen defects of less than or equal to 3%, and is doped with about 0.01 mole/cm3 to about 0.3 mole/cm3 of 3d transition metal. The metal oxide comprises indium oxide or titanium oxide. The 3d transition metal includes at least one 3d transition metal selected from the group consisting of chromium, cobalt, nickel, iron, manganese, and mixtures thereof.

Abstract translation: 薄膜晶体管基板包括绝缘板; 设置在绝缘板上的栅电极; 包含金属氧化物的半导体层，其中所述金属氧化物具有小于或等于3％的氧缺陷，并且其中所述金属氧化物包含约0.01mol / cm 3至约0.3mol / cm 3的3d过渡金属; 设置在所述栅极电极和所述半导体层之间的栅极绝缘层; 以及设置在半导体层上的源电极和漏电极。 还描述了显示基板。 金属氧化物具有小于或等于3％的氧缺陷，并且掺杂有约0.01摩尔/ cm3至约0.3摩尔/ cm3的3d过渡金属。 金属氧化物包括氧化铟或二氧化钛。 3d过渡金属包括选自铬，钴，镍，铁，锰及其混合物中的至少一种3d过渡金属。