公开(公告)号：US08487398B2

公开(公告)日：2013-07-16

申请号：US12835900

申请日：2010-07-14

申请人： Hongzhong Xu ,  Zhihong Zhang ,  Jiang-Kai Zuo

发明人： Hongzhong Xu ,  Zhihong Zhang ,  Jiang-Kai Zuo

IPC分类号： H01L21/70

CPC分类号： H01L29/94 ,  H01L29/66181

摘要： A semiconductor device includes an isolated p-type well, wherein the isolated p-type well is a first electrode of a capacitor device; a capacitor dielectric on the isolated p-type well; a p-type polysilicon electrode over the capacitor dielectric, wherein the p-type polysilicon electrode is a second electrode of the capacitor device; a first p-type contact region in the isolated p-type well, laterally extending from a first sidewall of the p-type polysilicon electrode; a second p-type contact region in the isolated p-type well, laterally extending from a second sidewall of the p-type polysilicon electrode, opposite the first sidewall of the p-type polysilicon electrode, wherein a portion of the isolated p-type well between the first and second p-type contact regions is under the p-type polysilicon electrode and the capacitor dielectric; and an n-type isolation region surrounding the isolated p-type well. This device may be conveniently coupled to a fringe capacitor.

摘要翻译： 半导体器件包括隔离的p型阱，其中隔离的p型阱是电容器器件的第一电极; 隔离p型阱上的电容器电介质; 电容器电介质上的p型多晶硅电极，其中p型多晶硅电极是电容器器件的第二电极; 分离的p型阱中的第一p型接触区，从p型多晶硅电极的第一侧壁横向延伸; 在隔离的p型阱中的第二p型接触区域，从p型多晶硅电极的第二侧壁横向延伸，与p型多晶硅电极的第一侧壁相对，其中一部分隔离的p型 第一和第二p型接触区之间的阱在p型多晶硅电极和电容器电介质之下; 以及围绕隔离p型阱的n型隔离区。 该装置可以方便地连接到边缘电容器。

公开(公告)号：US20120149354A1

公开(公告)日：2012-06-14

申请号：US13391747

申请日：2010-12-25

申请人： Yilun Ying ,  Liang Huo ,  Yu Jiang ,  Xing Liu ,  Yu Yao ,  Zhihong Zhang ,  Dawei Zhu ,  Yehui Zhang ,  Yang Luan ,  Song Yang

发明人： Yilun Ying ,  Liang Huo ,  Yu Jiang ,  Xing Liu ,  Yu Yao ,  Zhihong Zhang ,  Dawei Zhu ,  Yehui Zhang ,  Yang Luan ,  Song Yang

IPC分类号： H04W4/04 ,  H04W4/18 ,  G06F15/177

CPC分类号： G08G1/096716 ,  G08G1/096758 ,  G08G1/096775

摘要： A vehicle information system includes: a vehicle-mounted device, a network processing device and a service center which is adapted for providing service for the vehicle-mounted device. A service configuration channel is configured between the network processing device and the service center and is adapted for transmitting configuration data which are adapted for configuring service that is provided for the vehicle-mounted device. The service configuration channel is established on basis of connection to internet. A service channel system is configured between the vehicle-mounted device and the service center. A complete solution for providing information service may be provided by the vehicle information system, thereby improving the quality of user experience while using a vehicle.

摘要翻译： 车辆信息系统包括：适用于为车载装置提供服务的车载装置，网络处理装置和服务中心。 服务配置信道被配置在网络处理设备和服务中心之间，并适于发送适于配置为车载设备提供的服务的配置数据。 服务配置通道是基于与互联网的连接建立的。 在车载设备和服务中心之间配置服务通道系统。 可以由车辆信息系统提供用于提供信息服务的完整解决方案，从而在使用车辆时提高用户体验的质量。

公开(公告)号：US20120012970A1

公开(公告)日：2012-01-19

申请号：US12835900

申请日：2010-07-14

申请人： HONGZHONG XU ,  ZHIHONG ZHANG ,  JIANG-KAI ZUO

发明人： HONGZHONG XU ,  ZHIHONG ZHANG ,  JIANG-KAI ZUO

IPC分类号： H01L27/07 ,  H01L21/02 ,  H01L29/06

CPC分类号： H01L29/94 ,  H01L29/66181

摘要： A semiconductor device includes an isolated p-type well, wherein the isolated p-type well is a first electrode of a capacitor device; a capacitor dielectric on the isolated p-type well; a p-type polysilicon electrode over the capacitor dielectric, wherein the p-type polysilicon electrode is a second electrode of the capacitor device; a first p-type contact region in the isolated p-type well, laterally extending from a first sidewall of the p-type polysilicon electrode; a second p-type contact region in the isolated p-type well, laterally extending from a second sidewall of the p-type polysilicon electrode, opposite the first sidewall of the p-type polysilicon electrode, wherein a portion of the isolated p-type well between the first and second p-type contact regions is under the p-type polysilicon electrode and the capacitor dielectric; and an n-type isolation region surrounding the isolated p-type well. This device may be conveniently coupled to a fringe capacitor.

摘要翻译： 半导体器件包括隔离的p型阱，其中隔离的p型阱是电容器器件的第一电极; 隔离p型阱上的电容器电介质; 电容器电介质上的p型多晶硅电极，其中p型多晶硅电极是电容器器件的第二电极; 分离的p型阱中的第一p型接触区，从p型多晶硅电极的第一侧壁横向延伸; 在隔离的p型阱中的第二p型接触区域，从p型多晶硅电极的第二侧壁横向延伸，与p型多晶硅电极的第一侧壁相对，其中一部分隔离的p型 第一和第二p型接触区之间的阱在p型多晶硅电极和电容器电介质之下; 以及围绕隔离p型阱的n型隔离区。 该装置可以方便地连接到边缘电容器。

公开(公告)号：US09640635B2

公开(公告)日：2017-05-02

申请号：US14832139

申请日：2015-08-21

申请人： Zhihong Zhang ,  Daniel J. Blomberg ,  Hongning Yang ,  Jiang-Kai Zuo

发明人： Zhihong Zhang ,  Daniel J. Blomberg ,  Hongning Yang ,  Jiang-Kai Zuo

IPC分类号： H01L29/78 ,  H01L27/01 ,  H01L21/336 ,  H01L29/66 ,  H01L29/786 ,  H01L21/265 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L21/8234 ,  H01L29/36 ,  H01L27/088 ,  H01L21/761 ,  H01L21/762

CPC分类号： H01L29/66659 ,  H01L21/26513 ,  H01L21/761 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/0642 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/786 ,  H01L29/78615 ,  H01L29/78624 ,  H01L29/78654

摘要： A method of fabricating a transistor device having a channel of a first conductivity type formed during operation in a body region having a second conductivity type includes forming a first well region of the body region in a semiconductor substrate, performing a first implantation procedure to counter-dope the first well region with dopant of the first conductivity type to define a second well region of the body region, and performing a second implantation procedure to form a source region in the first well region and a drain region in the second well region.

公开(公告)号：US09490322B2

公开(公告)日：2016-11-08

申请号：US13748076

申请日：2013-01-23

申请人： Hongning Yang ,  Xin Lin ,  Zhihong Zhang ,  Jiang-Kai Zuo

发明人： Hongning Yang ,  Xin Lin ,  Zhihong Zhang ,  Jiang-Kai Zuo

IPC分类号： H01L29/94 ,  H01L29/08 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10

CPC分类号： H01L29/66681 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/7835

摘要： A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and spaced from one another along a first lateral dimension, and a drift region in the semiconductor substrate and through which charge carriers drift during operation upon application of a bias voltage between the source and drain regions. The drift region has a notched dopant profile in a second lateral dimension along an interface between the drift region and the drain region.

摘要翻译： 一种器件包括半导体衬底，半导体衬底中的源极和漏极区域以及沿着第一横向尺寸彼此间隔开的半导体衬底中的漂移区域，并且在施加偏置电压之前电荷载体在操作期间漂移 源极和漏极区域。 漂移区域沿着漂移区域和漏极区域之间的界面在第二横向维度上具有缺口掺杂剂分布。

公开(公告)号：US20150325565A1

公开(公告)日：2015-11-12

申请号：US14272027

申请日：2014-05-07

申请人： Hongning Yang ,  Xin Lin ,  Pete Rodriguez ,  Zhihong Zhang ,  Jiang-Kai Zuo

发明人： Hongning Yang ,  Xin Lin ,  Pete Rodriguez ,  Zhihong Zhang ,  Jiang-Kai Zuo

IPC分类号： H01L27/02 ,  H01L29/08 ,  H01L21/265 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/10

CPC分类号： H01L27/0248 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823418 ,  H01L27/0266 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1045 ,  H01L29/1079 ,  H01L29/1095 ,  H01L29/66575 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

摘要： A device includes a semiconductor substrate, a first constituent transistor including a first plurality of transistor structures in the semiconductor substrate connected in parallel with one another, and a second constituent transistor including a second plurality of transistor structures in the semiconductor substrate connected in parallel with one another. The first and second constituent transistors are disposed laterally adjacent to one another and connected in parallel with one another. Each transistor structure of the first plurality of transistor structures includes a non-uniform channel such that the first constituent transistor has a higher threshold voltage level than the second constituent transistor.

摘要翻译： 一种器件包括半导体衬底，第一组成晶体管，其包括彼此并联连接的半导体衬底中的第一多个晶体管结构;以及第二组成晶体管，包括在半导体衬底中并联连接的第二多个晶体管结构， 另一个。 第一和第二组成晶体管彼此横向相邻设置并彼此并联连接。 第一多个晶体管结构的每个晶体管结构包括非均匀沟道，使得第一构成晶体管具有比第二构成晶体管更高的阈值电压电平。

公开(公告)号：US09117841B2

公开(公告)日：2015-08-25

申请号：US14047348

申请日：2013-10-07

申请人： Zhihong Zhang ,  Daniel J. Blomberg ,  Hongning Yang ,  Jiang-Kai Zuo

发明人： Zhihong Zhang ,  Daniel J. Blomberg ,  Hongning Yang ,  Jiang-Kai Zuo

IPC分类号： H01L29/78 ,  H01L27/01 ,  H01L21/336 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L29/66659 ,  H01L21/26513 ,  H01L21/761 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/0642 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/786 ,  H01L29/78615 ,  H01L29/78624 ,  H01L29/78654

摘要： A device includes a semiconductor substrate, source and drain regions disposed in the semiconductor substrate, having a first conductivity type, and laterally spaced from one another, and a composite body region disposed in the semiconductor substrate and having a second conductivity type. The composite body region includes a first well region that extends laterally across the source and drain regions and a second well region disposed in the first well region. The drain region is disposed in the second well region such that charge carriers flow from the first well region into the second well region to reach the drain region. The second well region includes dopant of the first conductivity type to have a lower net dopant concentration level than the first well region. A pocket may be disposed in a drain extension region and configured to establish a depletion region along an edge of a gate structure.

摘要翻译： 一种器件包括半导体衬底，设置在半导体衬底中的源极和漏极区域，具有第一导电类型，并且彼此横向间隔开;以及复合体区域，设置在半导体衬底中并且具有第二导电类型。 复合体区域包括沿着源极和漏极区域横向延伸的第一阱区域和设置在第一阱区域中的第二阱区域。 漏极区域设置在第二阱区域中，使得载流子从第一阱区域流入第二阱区域以到达漏极区域。 第二阱区域包括具有比第一阱区域更低的净掺杂剂浓度水平的第一导电类型的掺杂剂。 凹槽可以设置在漏极延伸区域中并且被配置成沿着栅极结构的边缘建立耗尽区域。

公开(公告)号：US08853780B2

公开(公告)日：2014-10-07

申请号：US13465761

申请日：2012-05-07

申请人： Hongning Yang ,  Daniel J. Blomberg ,  Xu Cheng ,  Xin Lin ,  Won Gi Min ,  Zhihong Zhang ,  Jiang-Kai Zuo

发明人： Hongning Yang ,  Daniel J. Blomberg ,  Xu Cheng ,  Xin Lin ,  Won Gi Min ,  Zhihong Zhang ,  Jiang-Kai Zuo

IPC分类号： H01L29/66

CPC分类号： H01L29/063 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

摘要： A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate, a channel region in the semiconductor substrate between the source and drain regions through which charge carriers flow during operation from the source region to the drain region, and a drift region in the semiconductor substrate, on which the drain region is disposed, and through which the charge carriers drift under an electric field arising from application of a bias voltage between the source and drain regions. A PN junction along the drift region includes a first section at the drain region and a second section not at the drain region. The drift region has a lateral profile that varies such that the first section of the PN junction is shallower than the second section of the PN junction.

摘要翻译： 一种器件包括半导体衬底，半导体衬底中的源极和漏极区域，在源极和漏极区域之间的半导体衬底中的沟道区域，电荷载体在从源极区域到漏极区域的工作期间流过该沟道区域，以及漂移区域 其上设置有漏极区的半导体衬底，并且电荷载流子在源极和漏极区域之间施加偏压产生的电场下漂移。 沿着漂移区域的PN结包括在漏极区域处的第一部分和不在漏极区域的第二部分。 漂移区域具有变化的横向轮廓，使得PN结的第一部分比PN结的第二部分浅。

公开(公告)号：US20140209988A1

公开(公告)日：2014-07-31

申请号：US13756248

申请日：2013-01-31

申请人： Xin Lin ,  Hongning Yang ,  Zhihong Zhang ,  Jiang-Kai Zuo

发明人： Xin Lin ,  Hongning Yang ,  Zhihong Zhang ,  Jiang-Kai Zuo

IPC分类号： H01L29/66 ,  H01L27/088

CPC分类号： H01L29/66825 ,  H01L27/11558 ,  H01L29/7881

摘要： A multiple time programmable nonvolatile memory device having a single polysilicon memory cell includes a select transistor and a bitcell transistor. The bitcell transistor has asymmetrically configured source, drain, and channel regions including asymmetrically configured source-body and drain-body junctions. Compared with the drain-body junction, the impurity concentration gradient of the source-body junction is more gradual, which may significantly improve program disturb immunity. The bitcell transistor gate may be connected to an electrode of a coupling capacitor, but may be otherwise floating or Ohmically isolated. The floating gate of the bitcell is protected by a dielectric layer for potentially improved data retention.

摘要翻译： 具有单个多晶硅存储单元的多时间可编程非易失性存储器件包括选择晶体管和位单元晶体管。 位单元晶体管具有不对称配置的源极，漏极和沟道区域，包括不对称配置的源极体和漏极 - 体部结。 与漏 - 体结相比，源 - 体结的杂质浓度梯度更为平缓，可以显着提高程序的干扰免疫力。 位单元晶体管栅极可以连接到耦合电容器的电极，但是可以以浮置或欧姆隔离的方式。 位单元的浮动栅极由介电层保护，以便潜在地改善数据保持。

公开(公告)号：US20140203358A1

公开(公告)日：2014-07-24

申请号：US13748076

申请日：2013-01-23

申请人： Hongning Yang ,  Xin Lin ,  Zhihong Zhang ,  Jiang-Kai Zuo

发明人： Hongning Yang ,  Xin Lin ,  Zhihong Zhang ,  Jiang-Kai Zuo

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/66681 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/7835

摘要： A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and spaced from one another along a first lateral dimension, and a drift region in the semiconductor substrate and through which charge carriers drift during operation upon application of a bias voltage between the source and drain regions. The drift region has a notched dopant profile in a second lateral dimension along an interface between the drift region and the drain region.

摘要翻译： 一种器件包括半导体衬底，半导体衬底中的源极和漏极区域以及沿着第一横向尺寸彼此间隔开的半导体衬底中的漂移区域，并且在施加偏置电压之前电荷载体在操作期间漂移 源极和漏极区域。 漂移区域沿着漂移区域和漏极区域之间的界面在第二横向维度上具有缺口掺杂剂分布。