公开(公告)号：US12019560B2

公开(公告)日：2024-06-25

申请号：US17556431

申请日：2021-12-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Sooraj Puthoor ,  Muhammad Amber Hassaan ,  Ashwin Aji ,  Michael L. Chu ,  Nuwan Jayasena

IPC: G06F12/10 ,  G06F12/02 ,  G06F12/1009 ,  G06F12/1045 ,  G06F12/1072 ,  G06F13/16

CPC classification number: G06F12/1072 ,  G06F12/0238 ,  G06F12/1009 ,  G06F12/1054 ,  G06F12/1063 ,  G06F13/1673 ,  G06F2212/7201

Abstract: Process isolation for a PIM device includes: receiving, from a process, a call to allocate a virtual address space where the process stores a PIM configuration context; allocating the virtual address space including mapping a physical address space including PIM device configuration registers to the virtual address space only if the physical address space is not mapped to another process's virtual address space; and programming the PIM device configuration space according to the configuration context. When a PIM command is executed, a translation mechanism determines whether there is a valid mapping of a virtual address of the PIM command to a physical address of a PIM resource, such as a LIS entry. If a valid mapping exists, the translation is completed and the resource is accessed, but if there is not a valid mapping, the translation fails and the process is blocked from accessing the PIM resource.

公开(公告)号：US11934698B2

公开(公告)日：2024-03-19

申请号：US17556503

申请日：2021-12-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Sooraj Puthoor ,  Muhammad Amber Hassaan ,  Ashwin Aji ,  Michael L. Chu ,  Nuwan Jayasena

IPC: G06F3/06 ,  G06F7/575

CPC classification number: G06F3/0659 ,  G06F3/0622 ,  G06F3/0631 ,  G06F3/0656 ,  G06F3/0679 ,  G06F7/575

Abstract: Process isolation for a PIM device through exclusive locking includes receiving, from a process, a call requesting ownership of a PIM device. The request includes one or more PIM configuration parameters. The exclusive locking technique also includes granting the process ownership of the PIM device responsive to determining that ownership is available. The PIM device is configured according to the PIM configuration parameters.

公开(公告)号：US20230409238A1

公开(公告)日：2023-12-21

申请号：US17845263

申请日：2022-06-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Shaizeen Aga ,  Nuwan Jayasena

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0673 ,  G06F3/0604

Abstract: An approach is provided for processing near-memory processing commands, e.g., PIM commands, using PIM register definition data that defines multiple combinations of source and/or destination registers to be used to process PIM commands. A particular combination of source and/or destination registers to be used to process a PIM command is specified by the PIM command or determined by a near-memory processing element processing the PIM command. According to another implementation, the PIM register definition data specifies an initial combination of source and/or destination registers and one or more update functions for each PIM command. A near-memory processing element processes a PIM command using the initial combination of source and/or destination registers and uses the one or more update functions to update the combination of source and/or destination registers to be used the next time the PIM command is processed.

公开(公告)号：US11669271B2

公开(公告)日：2023-06-06

申请号：US16848920

申请日：2020-04-15

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Anirban Nag ,  Nuwan Jayasena ,  Shaizeen Aga

IPC: G06F3/06 ,  G06F9/448 ,  G06F9/48

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0614 ,  G06F3/0673 ,  G06F9/4498 ,  G06F9/4881

Abstract: Memory operations using compound memory commands, including: receiving, by a memory module, a compound memory command indicating one or more operations to be applied to each portion of a plurality of portions of contiguous memory in the memory module; generating, based on the compound memory command, a plurality of memory commands to apply the one or more operations to each portion of the plurality of portions of contiguous memory; and executing the plurality of memory commands.

公开(公告)号：US20230021492A1

公开(公告)日：2023-01-26

申请号：US17385783

申请日：2021-07-26

Applicant: Advanced Micro Devices, Inc.

Inventor： Shaizeen Aga ,  Nuwan Jayasena ,  John Kalamatianos

IPC: G06F12/0891 ,  G06F12/0811 ,  G06F12/02 ,  G06F13/16

Abstract: A technical solution to the technical problem of how to support memory-centric operations on cached data uses a novel memory-centric memory operation that invokes write back functionality on cache controllers and memory controllers. The write back functionality enforces selective flushing of dirty, i.e., modified, cached data that is needed for memory-centric memory operations from caches to the completion level of the memory-centric memory operations, and updates the coherence state appropriately at each cache level. The technical solution ensures that commands to implement the selective cache flushing are ordered before the memory-centric memory operation at the completion level of the memory-centric memory operation.

公开(公告)号：US11309911B2

公开(公告)日：2022-04-19

申请号：US16542872

申请日：2019-08-16

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander D. Breslow ,  Nuwan Jayasena ,  John Kalamatianos

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  H03M7/40 ,  G06F7/08 ,  G06F3/06

Abstract: A data processing platform, method, and program product perform compression and decompression of a set of data items. Suffix data and a prefix are selected for each respective data item in the set of data items based on data content of the respective data item. The set of data items is sorted based on the prefixes. The prefixes are encoded by querying multiple encoding tables to create a code word containing compressed information representing values of all prefixes for the set of data items. The code word and suffix data for each of the data items are stored in memory. The code word is decompressed to recover the prefixes. The recovered prefixes are paired with their respective suffix data.

公开(公告)号：US20220091974A1

公开(公告)日：2022-03-24

申请号：US17031518

申请日：2020-09-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan Jayasena ,  Shaizeen Aga

IPC: G06F12/02 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/0868 ,  G06F15/173

Abstract: A processing device and methods of controlling remote persistent writes are provided. Methods include receiving an instruction of a program to issue a persistent write to remote memory. The methods also include logging an entry in a local domain when the persistent write instruction is received and providing a first indication that the persistent write will be persisted to the remote memory. The methods also include executing the persistent write to the remote memory and providing a second indication that the persistent write to the remote memory is completed. The methods also include providing the first and second indications when it is determined not to execute the persistent write according to global ordering and providing the second indication without providing the first indication when it is determined to execute the persistent write to remote memory according to global ordering.

公开(公告)号：US11262949B2

公开(公告)日：2022-03-01

申请号：US16885677

申请日：2020-05-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Johnathan Alsop ,  Shaizeen Aga ,  Nuwan Jayasena

IPC: G06F3/06 ,  G06F12/00 ,  G06F13/00

Abstract: An approach is provided for reducing command bus traffic between memory controllers and PIM-enabled memory modules using special PIM commands. The term “special PIM command” is used herein to describe embodiments and refers to a PIM command for which the corresponding module-specific command information is provided to memory modules via a non-command bus data path. A memory controller generates and issues a special PIM command to multiple PIM-enabled memory modules via a command bus and provides module-specific command information (e.g., address information) for the special PIM command to the PIM-enabled memory modules via the non-command bus data path that is shared by the PIM-enabled memory modules and the memory controller.

公开(公告)号：US11049794B2

公开(公告)日：2021-06-29

申请号：US14194701

申请日：2014-03-01

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Manish Arora ,  Nuwan Jayasena

IPC: H01L23/373 ,  H01L23/427 ,  H05K1/02 ,  H01L23/00 ,  H05K3/46 ,  H05K3/34

Abstract: Various circuit board embodiments are disclosed. In one aspect, an apparatus is provided that includes a circuit board and a first phase change material pocket positioned on or in the circuit board and contacting a surface of the circuit board.

公开(公告)号：US10990453B2

公开(公告)日：2021-04-27

申请号：US15952149

申请日：2018-04-12

Applicant: Advanced Micro Devices, Inc.

Inventor： Amin Farmahini-Farahani ,  David A. Roberts ,  Nuwan Jayasena

IPC: G06F9/52

Abstract: A memory fence or other similar operation is executed with reduced latency. An early fence operation is executed and acts as a hint to the processor executing the thread that executes the fence. This hint causes the processor to begin performing sub-operations for the fence earlier than if no such hint were executed. Examples of sub-operations for the fence include operations to make data written to by writes prior to the fence operation available to other threads. A resolving fence, which occurs after the early fence, performs the remaining sub-operations for the fence. By triggering some or all of the sub-operations for a memory fence that will occur in the future, the early fence operation reduces the amount of latency associated with that memory fence operation.