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公开(公告)号：US11709745B2
公开(公告)日：2023-07-25
申请号：US17588779
申请日：2022-01-31
Applicant: Advanced Micro Devices, Inc.
Inventor： Sergey Blagodurov , Michael Ignatowski , Vilas Sridharan
CPC classification number: G06F11/2094 , G06F2201/82
Abstract: A method includes, in response to a memory error indication indicating an uncorrectable error in a faulted segment, associating in a remapping table the faulted segment with a patch segment in a patch memory region, and in response to receiving from a processor a memory access request directed to the faulted segment, servicing the memory access request from the patch segment by performing the requested memory access at the patch segment based on a patch segment address identifying the location of the patch segment. The patch segment address is determined from the remapping table and corresponds to a requested memory address specified by the memory access request.
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公开(公告)号：US20210165721A1
公开(公告)日：2021-06-03
申请号：US16700993
申请日：2019-12-02
Applicant: Advanced Micro Devices, Inc.
Inventor： Sergey Blagodurov , Michael Ignatowski , Vilas Sridharan
IPC: G06F11/20
Abstract: A method includes reserving memory capacity in a first memory device as patch memory region for backing faulted memory, receiving a memory error indication indicating an uncorrectable error in a faulted segment in a second memory device and, in response to the memory error indication, associating in a remapping table the faulted segment with a patch segment in the patch memory region. The faulted segment is smaller than a memory page size of the second memory device. The method also includes, in response to receiving a memory access request directed to the faulted memory segment, servicing the memory access request from the patch segment by querying the remapping table to determine a patch segment address corresponding to a requested memory address, where the patch segment address identifies the location of the patch segment, and based on the patch segment address, performing the requested memory access at the patch segment.
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公开(公告)号：US20210049062A1
公开(公告)日：2021-02-18
申请号：US16705913
申请日：2019-12-06
Applicant: Advanced Micro Devices, Inc.
Inventor： Kedarnath Balakrishnan , James R. Magro , Kevin Michael Lepak , Vilas Sridharan
Abstract: A data processing system includes a memory channel, a memory coupled to the memory channel, and a data processor. The data processor is coupled to the memory channel and accesses the memory over the memory channel using a packet structure defining a plurality of commands and having corresponding address bits, data bits, and user bits. The data processor communicates with the memory over the memory channel using a first type of error code. In response to a write access request, the data processor calculates a different, second type of error code and appends each bit of the second type of error code as a corresponding one of the user bits. The memory stores the user bits in the memory in response to a write command, and transfers the user bits to the data processor in a read response packet in response to a read command.
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公开(公告)号：US20190034251A1
公开(公告)日：2019-01-31
申请号：US15662524
申请日：2017-07-28
Applicant: Advanced Micro Devices, Inc.
Inventor： Vilas Sridharan , David A. Roberts
Abstract: Described herein are a method and apparatus for memory vulnerability prediction. A memory vulnerability predictor predicts the reliability of a memory region when it is first accessed, based on past program history. The memory vulnerability predictor uses a table to store reliability predictions and predicts reliability needs of a new memory region. A memory management module uses the reliability information to make decisions, (such as to guide memory placement policies in a heterogeneous memory system).
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公开(公告)号：US09274904B2
公开(公告)日：2016-03-01
申请号：US13920524
申请日：2013-06-18
Applicant: Advanced Micro Devices, Inc.
Inventor： Alexander Lyashevsky , Sudhanva Gurumurthi , Vilas Sridharan
CPC classification number: G06F11/00 , G06F9/3851 , G06F9/52 , G06F11/1608 , G06F11/1633 , G06F11/1637 , G06F11/1654 , G06F11/1687 , G06F11/202 , G06F11/2038 , G06F11/2041 , G06F11/2048 , G06F2201/825 , G06F2201/83
Abstract: A system, method and computer program product to execute a first and a second work-group, and compare the signature variables of the first work-group to the signature variables of the second work-group via a synchronization mechanism. The first and the second work-group are mapped to an identifier via software. This mapping ensures that the first and second work-groups execute exactly the same data for exactly the same code without changes to the underlying hardware. By executing the first and second work-groups independently, the underlying computation of the first and second work-groups can be verified. Moreover, system performance is not substantially affected because the execution results of the first and second work-groups are compared only at specified comparison points.
Abstract translation: 一种用于执行第一和第二工作组的系统，方法和计算机程序产品，并且经由同步机制将第一工作组的签名变量与第二工作组的签名变量进行比较。 第一个和第二个工作组通过软件映射到一个标识符。 此映射确保第一个和第二个工作组对完全相同的代码执行完全相同的数据，而不会更改底层硬件。 通过独立地执行第一和第二工作组，可以验证第一和第二工作组的基础计算。 此外，由于第一和第二工作组的执行结果仅在指定的比较点进行比较，系统性能基本上不受影响。
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Patent Agency Ranking
公开(公告)号：US09047192B2
公开(公告)日：2015-06-02
申请号：US13724987
申请日：2012-12-21
Applicant: Advanced Micro Devices, Inc.
Inventor： Vilas Sridharan , Sudhanva Gurumurthi
CPC classification number: G06F11/08 , G06F11/1004 , G06F11/167 , G06F17/30743
Abstract: A system and method for optimizing redundant output verification, are provided. A hardware-based store fingerprint buffer receives multiple instances of output from multiple instances of computation. The store fingerprint buffer generates a signature from the content included in the multiple instances of output. When a barrier is reached, the store fingerprint buffer uses the signature to verify the content is error-free.
Abstract translation: 提供了一种用于优化冗余输出验证的系统和方法。 基于硬件的商店指纹缓冲器从多个计算实例接收多个输出实例。 存储指纹缓冲区从包含在输出的多个实例中的内容生成签名。 当达到屏障时，商店指纹缓冲区使用签名来验证内容是否无错误。
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公开(公告)号：US20250004873A1
公开(公告)日：2025-01-02
申请号：US18678596
申请日：2024-05-30
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Sudhanva Gurumurthi , Vilas Sridharan
Abstract: A processing system includes a processing device coupled to a memory configured to check for and correct faults in requested data. In response to correcting the faults of the requested data, the memory sends the corrected data and unused check bits to the processing device as a plurality of fetch returns. The memory also sends a parity fetch based on the corrected data and one or more operations to the processing device. After receiving the plurality of fetch returns and the unused check bits, the processing device checks each fetch return for faults based on the unused check bits. In response to determining that a fetch return includes a fault, the processing device erases the fetch return and reconstructs the fetch return based on one or more other received fetch returns and the parity fetch.
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28.发明公开公开(公告)号：US20240211362A1
公开(公告)日：2024-06-27
申请号：US18089135
申请日：2022-12-27
Applicant: Advanced Micro Devices, Inc.
Inventor： Vilas Sridharan , Hanbing Liu , Francisco L. Duran
CPC classification number: G06F11/261 , G06F11/0784 , G06F11/0787
Abstract: An exemplary system includes and/or represents an agent and a machine check architecture. In one example, the machine check architecture includes and/or represents at least one circuit configured to report errors via at least one reporting register. In this example, the machine check architecture also includes and/or represents at least one error-injection register configured to cause the circuit to inject at least one fabricated error report into the reporting register in response to a write operation performed by the agent on at least one bit of the error-injection register. Various other devices, systems, and methods are also disclosed.
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公开(公告)号：US20240143440A1
公开(公告)日：2024-05-02
申请号：US17977001
申请日：2022-10-31
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Sudhanva Gurumurthi , Vilas Sridharan , Majed Valad Beigi
IPC: G06F11/10 , G06F11/07 , G06F12/1027
CPC classification number: G06F11/1068 , G06F11/0793 , G06F12/1027
Abstract: A processing system employs techniques for enhancing dynamic random access memory (DRAM) page retirement to facilitate identification and retirement of pages affected by multi-page DRAM faults. In response to detecting an uncorrectable error at a first page of DRAM, the processing system identifies a second page of the DRAM for potential retirement based on one or more of physical proximity to the first page, inclusion in a range of addresses stored at a fault map that tracks addresses of DRAM pages having detected faults, and predicting a set of pages to check for faults based on misses at a translation lookaside buffer (TLB).
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公开(公告)号：US11966283B1
公开(公告)日：2024-04-23
申请号：US18072650
申请日：2022-11-30
Applicant: Advanced Micro Devices, Inc.
Inventor： Divya Madapusi Srinivas Prasad , Sudhanva Gurumurthi , Yasuko Eckert , Jeffrey Richard Rearick , Sankaranarayanan Gurumurthy , Amitabh Mehra , Shidhartha Das , Alex W. Schaefer , Vikram Ramachandra , Vilas Sridharan
CPC classification number: G06F11/0793 , G06F11/07 , G06F1/30 , G06F11/0721
Abstract: An exemplary computing device includes a plurality of circuits and/or a plurality of in-situ monitors configured to generate outputs that indicate one or more operating conditions of the circuits. The computing device also includes a system management unit configured to detect a potentially faulty voltage-to-frequency ratio implemented by one of the circuits based at least in part on one or more of the outputs. The system management unit is also configured to modify the potentially faulty voltage-to-frequency ratio based at least in part on one or more of the outputs. Various other devices, systems, and methods are also disclosed.
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