公开(公告)号：US20140310437A1

公开(公告)日：2014-10-16

申请号：US13861696

申请日：2013-04-12

Applicant: APPLE INC.

Inventor： Gurjeet S. Saund ,  Deniz Balkan ,  Munetoshi Fukami

IPC: G06F13/37

CPC classification number: G06F13/37 ,  G06F13/36

Abstract: In an embodiment, an arbiter may implement a deficit-weighted round-robin scheme having a delayed weight-reload mechanism. The delay may be greater than or equal to a ratio of the fabric clock to a slower clock associated with one or more sources that have no transactions but that have unconsumed weights (or another measure of difference in transaction rate). If a transaction is provided from the one or more sources during the delay, the reload of the weights may be prevented. In some embodiments, the arbiter may be augmented to improve usage of the bandwidth on an interface in which some transactions may be limited for a period of time. The arbiter may implement a first pointer that performs round robin arbitration. If the first pointer is indicating a source whose transaction is temporarily blocked, a second pointer may search forward from the current position of the main pointer to locate a non-blocked transaction.

Abstract translation: 在一个实施例中，仲裁器可以实现具有延迟加权重载机制的赤字加权循环方案。 所述延迟可以大于或等于所述织物时钟与不具有交易但具有未消耗权重（或交易速率的差别的另一措施）的一个或多个源相关联的较慢时钟的比率。 如果在延迟期间从一个或多个源提供事务，则可以防止权重的重新加载。 在一些实施例中，仲裁器可以被扩充以改善在一些接口上的带宽的使用，其中一些事务可能被限制一段时间。 仲裁器可以实现执行循环仲裁的第一个指针。 如果第一指针指示其事务被临时阻止的源，则第二指针可以从主指针的当前位置向前搜索以定位未阻塞的事务。

公开(公告)号：US20140241376A1

公开(公告)日：2014-08-28

申请号：US13778482

申请日：2013-02-27

Applicant: APPLE INC.

Inventor： Deniz Balkan ,  Gurjeet S Saund ,  Kevin C Wong ,  Munetoshi Fukami

IPC: H04L12/56

CPC classification number: H04L47/6275 ,  H04L47/6205 ,  H04L47/6295 ,  H04W28/10

Abstract: Various embodiments of a method and apparatus for controlling transaction flow in a communications fabric is disclosed. In one embodiment, an IC includes a communications fabric connecting multiple agents to one another. Each agent may include an interface coupling itself to at least one other agent. Each interface may include multiple queues for storing information corresponding to pending transactions. Also included in each interface is an arbitration unit and control logic. The control logic may determine which transactions are presented to the arbitration unit for arbitration. In one embodiment, the control logic may inhibit certain transactions from being presented to the arbitration unit so that other higher priority transactions may advance. In another embodiment, the control logic may reduce the priority level of some transactions for arbitration purposes to prevent the blocking of other higher priority transactions.

Abstract translation: 公开了用于控制通信结构中的事务流的方法和装置的各种实施例。 在一个实施例中，IC包括将多个代理彼此连接的通信结构。 每个代理可以包括将自身耦合到至少一个其他代理的接口。 每个接口可以包括用于存储对应于待处理事务的信息的多个队列。 每个接口中还包括一个仲裁单元和控制逻辑。 控制逻辑可以确定哪些事务被呈现给仲裁单元进行仲裁。 在一个实施例中，控制逻辑可以禁止某些交易被呈现给仲裁单元，使得其他更高优先级的事务可以提前。 在另一个实施例中，控制逻辑可以减少用于仲裁目的的一些交易的优先级，以防止阻塞其他更高优先级的事务。

公开(公告)号：US20140108688A1

公开(公告)日：2014-04-17

申请号：US13653151

申请日：2012-10-16

Applicant: APPLE INC.

Inventor： Manu Gulati ,  Erik P. Machnicki ,  Deniz Balkan

IPC: G06F13/24

CPC classification number: G06F13/24 ,  G06F13/26 ,  Y02D10/14

Abstract: In an embodiment, a system includes at least one peripheral device, an interrupt controller, a memory controller, at least one CPU, and an interrupt message circuit coupled to the peripheral device. The interrupt message circuit may be coupled to receive the interrupt signal from the peripheral device, and may be configured to generate an interrupt message for transmission on a communication fabric. In some embodiments, there may be multiple peripherals which have independent paths through the fabric for memory operations to the memory controller. Each such peripheral may be coupled to an instance of the interrupt message circuit. In an embodiment, the interrupt is level sensitive. The interrupt message circuit may be configured to transmit interrupt set messages an interrupt clear messages to the interrupt controller, to indicate the levels.

Abstract translation: 在一个实施例中，系统包括耦合到外围设备的至少一个外围设备，中断控制器，存储器控制器，至少一个CPU以及中断消息电路。 中断消息电路可以被耦合以从外围设备接收中断信号，并且可以被配置为生成用于在通信结构上传输的中断消息。 在一些实施例中，可以存在多个外围设备，其具有通过该结构的独立路径，用于存储器操作到存储器控制器。 每个这样的外设可以耦合到中断消息电路的一个实例。 在一个实施例中，中断是电平敏感的。 中断消息电路可以被配置为向中断控制器发送中断设置消息中断清除消息以指示电平。

公开(公告)号：US11537538B2

公开(公告)日：2022-12-27

申请号：US17242051

申请日：2021-04-27

Applicant: Apple Inc.

Inventor： Harshavardhan Kaushikkar ,  Christopher D. Shuler ,  Srinivasa Rangan Sridharan ,  Yu Zhang ,  Kaushik Kannan ,  Deniz Balkan

IPC: G06F11/34 ,  G06F13/16 ,  G06F13/40

Abstract: In one embodiment, a cache coherent system includes one or more agents (e.g., coherent agents) that may cache data used by the system. The system may include a point of coherency in a memory controller in the system, and thus the agents may transmit read requests to the memory controller to coherently read data. The point of coherency may determine if the data is cached in another agent, and may transmit a copy back request to the other agent if the other agent has modified the data. The system may include an interconnect between the agents and the memory controller. At a point on the interconnect at which traffic from the agents converges, a copy back response may be converted to a fill for the requesting agent.

公开(公告)号：US11016913B1

公开(公告)日：2021-05-25

申请号：US16834148

申请日：2020-03-30

Applicant: Apple Inc.

Inventor： Harshavardhan Kaushikkar ,  Christopher D. Shuler ,  Srinivasa Rangan Sridharan ,  Yu Zhang ,  Kaushik Kannan ,  Deniz Balkan

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/40

Abstract: In one embodiment, a cache coherent system includes one or more agents (e.g. coherent agents) that may cache data used by the system. The system may include a point of coherency in a memory controller in the system, and thus the agents may transmit read requests to the memory controller to coherently read data. The point of coherency may determine if the data is cached in another agent, and may transmit a copy back request to the other agent if the other agent has modified the data. The system may include an interconnect between the agents and the memory controller. At a point on the interconnect at which traffic from the agents converges, a copy back response may be converted to a fill for the requesting agent.

公开(公告)号：US10423558B1

公开(公告)日：2019-09-24

申请号：US16058433

申请日：2018-08-08

Applicant: Apple Inc.

Inventor： Shawn Munetoshi Fukami ,  Yiu Chun Tse ,  David L. Trawick ,  Hengsheng Geng ,  Jaideep Dastidar ,  Vinodh R. Cuppu ,  Deniz Balkan

IPC: G06F3/06 ,  G06F13/40 ,  G06F13/16 ,  G06F13/362 ,  G06F9/54 ,  G06F13/18

Abstract: A system and method for efficiently routing data in a communication fabric. A computing system includes a fabric for routing data among one or more agents and a memory controller for system memory. The fabric includes multiple hierarchical clusters with a split topology where the data links are physically separated from the control links. A given cluster receives a write command and associated write data, and stores them in respective buffers. The given cluster marks the write command as a candidate to be issued to the memory controller when it is determined the write data will arrive ahead of the write command at the memory controller after being issued. The given cluster prevents the write command from becoming a candidate to be issued when it is determined the write data may not arrive ahead of the write command at the memory controller.

公开(公告)号：US20180067877A1

公开(公告)日：2018-03-08

申请号：US15257527

申请日：2016-09-06

Applicant: Apple Inc.

Inventor： Deniz Balkan

IPC: G06F13/16 ,  G06F13/42 ,  G06F13/40

CPC classification number: G06F13/1642 ,  G06F13/1673 ,  G06F13/4022 ,  G06F13/4282

Abstract: Systems and methods for maintaining an order of read and write transactions for each source through a bridge in a bus fabric are disclosed. The bridge provides a connection from a first bus to a second bus within the bus fabric. The first bus has a single path for read and write transactions and the second bus has separate paths for read and write transactions. The bridge allows writes to pass reads for a given source, but prevents reads from passing writes. The bridge forwards a write transaction out of the bridge when the write transaction is available for forwarding. The bridge forwards a read transaction from a given source out of the bridge when there are no outstanding write transactions for the given source that are older than the read transaction. The bridge prevents forwarding the read transaction from the given source out of the bridge when there are outstanding write transactions that are older than the read transaction for the given source.

公开(公告)号：US09280503B2

公开(公告)日：2016-03-08

申请号：US13861696

申请日：2013-04-12

Applicant: Apple Inc.

Inventor： Gurjeet S. Saund ,  Deniz Balkan ,  Munetoshi Fukami

IPC: G06F13/37 ,  G06F13/36

CPC classification number: G06F13/37 ,  G06F13/36

Abstract: In an embodiment, an arbiter may implement a deficit-weighted round-robin scheme having a delayed weight-reload mechanism. The delay may be greater than or equal to a ratio of the fabric clock to a slower clock associated with one or more sources that have no transactions but that have unconsumed weights (or another measure of difference in transaction rate). If a transaction is provided from the one or more sources during the delay, the reload of the weights may be prevented. In some embodiments, the arbiter may be augmented to improve usage of the bandwidth on an interface in which some transactions may be limited for a period of time. The arbiter may implement a first pointer that performs round robin arbitration. If the first pointer is indicating a source whose transaction is temporarily blocked, a second pointer may search forward from the current position of the main pointer to locate a non-blocked transaction.

Abstract translation: 在一个实施例中，仲裁器可以实现具有延迟加权重载机制的赤字加权循环方案。 所述延迟可以大于或等于所述织物时钟与不具有交易但具有未消耗权重（或交易速率的差别的另一措施）的一个或多个源相关联的较慢时钟的比率。 如果在延迟期间从一个或多个源提供事务，则可以防止权重的重新加载。 在一些实施例中，仲裁器可以被扩充以改善在一些接口上的带宽的使用，其中一些事务可能被限制一段时间。 仲裁器可以实现执行循环仲裁的第一个指针。 如果第一指针指示其事务被临时阻止的源，则第二指针可以从主指针的当前位置向前搜索以定位未阻塞的事务。

公开(公告)号：US09229896B2

公开(公告)日：2016-01-05

申请号：US13724886

申请日：2012-12-21

Applicant: Apple Inc.

Inventor： Deniz Balkan ,  Gurjeet S. Saund

IPC: G06F13/36 ,  G06F13/40

CPC classification number: G06F13/4027 ,  G06F13/4059 ,  G06F2213/0038

Abstract: Systems and methods for maintaining an order of read and write transactions for each source through a bridge in a bus fabric. The bridge provides a connection from a first bus to a second bus within the bus fabric. The first bus has a single path for read and write transactions and the second bus has separate paths for read and write transactions. The bridge maintains a pair of counters for each source in a SoC to track the numbers of outstanding read and write transactions. The bridge prevents a read transaction from being forwarded to the second bus if the corresponding write counter is non-zero, and the bridge prevents a write transaction from being forwarded to the second bus if the corresponding read counter is non-zero.

Abstract translation: 用于通过总线结构中的桥梁维护每个源的读取和写入事务顺序的系统和方法。 该桥提供从总线结构中的第一总线到第二总线的连接。 第一个总线具有读取和写入事务的单一路径，第二个总线具有用于读取和写入事务的独立路径。 该桥在SoC中为每个源保留一对计数器，以跟踪未完成的读写事务的数量。 如果相应的写计数器不为零，桥将阻止读事务被转发到第二总线，如果相应的读计数器不为零，桥将阻止写事务被转发到第二总线。

公开(公告)号：US09229894B2

公开(公告)日：2016-01-05

申请号：US13859000

申请日：2013-04-09

Applicant: Apple Inc.

Inventor： Deniz Balkan ,  Gurjeet S Saund ,  Joseph P Bratt ,  Kevin C Wong ,  Manu Gulati ,  Rohit K Gupta

IPC: G06F13/42 ,  G06F3/00 ,  G06F13/36 ,  G06F13/38

CPC classification number: G06F13/385

Abstract: Embodiments of a bridge circuit and system are disclosed that may allow converting transactions from one communication protocol to another. The bridge circuit may be coupled to a first bus employing a first communication protocol, and a second bus employing a second communication protocol. The second bus may include a plurality of virtual channels. The bridge circuit may be configured to receive transactions over the first bus, and convert the transactions to the second communication protocol, and to assign the converted transaction to one of the plurality of virtual channels. The bridge circuit may be further configured store the converted transaction. A plurality of limited throughput signals may be generated by the bridge circuit dependent upon a number of available credits for the plurality of virtual channels.

Abstract translation: 公开了桥接电路和系统的实施例，其可以允许将事务从一个通信协议转换到另一个通信协议。 桥接电路可以耦合到采用第一通信协议的第一总线，以及采用第二通信协议的第二总线。 第二总线可以包括多个虚拟通道。 桥接电路可以被配置为通过第一总线接收事务，并将事务转换为第二通信协议，并将转换的事务分配给多个虚拟通道中的一个。 可以进一步配置桥接电路来存储转换的事务。 取决于多个虚拟信道的可用信用数量，桥电路可以产生多个有限吞吐量信号。