公开(公告)号：US10198364B2

公开(公告)日：2019-02-05

申请号：US15271102

申请日：2016-09-20

Applicant: Apple Inc.

Inventor： Saurabh Garg ,  Karan Sanghi ,  Vladislav Petkov ,  Haining Zhang

IPC: G06F12/00 ,  G06F12/14 ,  G06F12/1081

Abstract: Methods and apparatus for registering and handling access violations of host memory. In one embodiment, a peripheral processor receives one or more window registers defining an extent of address space accessible from a host processor; responsive to an attempt to access an extent of address space outside of the extent of accessible address space, generates an error message; stores the error message within a violation register; and resumes operation of the peripheral processor upon clearance of the stored error message.

公开(公告)号：US20170215145A1

公开(公告)日：2017-07-27

申请号：US15008229

申请日：2016-01-27

Applicant: APPLE INC.

Inventor： Richard M. Solotke ,  Saurabh Garg ,  Haining Zhang

IPC: H04W52/02

CPC classification number: H04W52/0235 ,  Y02D70/1262 ,  Y02D70/1264 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/146 ,  Y02D70/162 ,  Y02D70/166

Abstract: Methods and apparatus for limiting wake requests from one device to one or more other devices. In one embodiment, the requests are from a peripheral processor to a host processor within an electronic device such as a mobile smartphone or tablet which has power consumption requirements or considerations associated therewith. In one implementation, the peripheral processor includes a wake-limiting procedure encoded in e.g., its software or firmware, the procedure mitigating or preventing continuous and/or overly repetitive “wake” requests from the peripheral processor.

公开(公告)号：US10853272B2

公开(公告)日：2020-12-01

申请号：US16259543

申请日：2019-01-28

Applicant: Apple Inc.

Inventor： Saurabh Garg ,  Karan Sanghi ,  Vladislav Petkov ,  Haining Zhang

IPC: G06F12/14 ,  G06F12/1081

Abstract: Methods and apparatus for registering and handling access violations of host memory. In one embodiment, a peripheral processor receives one or more window registers defining an extent of address space accessible from a host processor; responsive to an attempt to access an extent of address space outside of the extent of accessible address space, generates an error message; stores the error message within a violation register; and resumes operation of the peripheral processor upon clearance of the stored error message.

公开(公告)号：US20190377703A1

公开(公告)日：2019-12-12

申请号：US16450767

申请日：2019-06-24

Applicant: Apple Inc.

Inventor： Vladislav Petkov ,  Saurabh Garg ,  Karan Sanghi ,  Haining Zhang

IPC: G06F15/17 ,  G06F13/42 ,  H04W4/80

Abstract: Methods and apparatus for data transmissions over an inter-processor communication (IPC) link between two (or more) independently operable processors. In one embodiment, the IPC link is configured to enable an independently operable processor to transact data to another independently operable processor, while obviating transactions (such as via direct memory access) by encapsulating a payload within a data structure. For example, a host processor may insert the payload into a transfer descriptor (TD), and transmit the TD to a peripheral processor. The host processor may also include a head index and/or a tail index within a doorbell message sent to the peripheral processor, obviating another access of memory. The peripheral processor may perform similar types of transactions via a completion descriptor (CD) sent to the host processor. In some variants, the peripheral may be a Bluetooth-enabled device optimized for low-latency, low-power, and/or low-throughput transactions.

公开(公告)号：US10425137B2

公开(公告)日：2019-09-24

申请号：US15482236

申请日：2017-04-07

Applicant: Apple Inc.

Inventor： Ming Hu ,  Haining Zhang ,  Xueting Liu

IPC: H04B7/06 ,  H04B1/3827 ,  H01Q1/24 ,  H01Q21/28 ,  H04B17/11 ,  H01Q3/24 ,  H03C7/02

Abstract: The disclosed embodiments provide a system that uses a first antenna and a second antenna in a portable electronic device. During operation, the system receives a request to switch from the first antenna to the second antenna to transmit a signal to a cellular receiver. Next, the system loads a set of radio-frequency (RF) calibration values for the second antenna. Finally, the system performs the switch from the first antenna to the second antenna to transmit the signal, wherein the second antenna is operated using the RF calibration values after the switch.

公开(公告)号：US10268261B2

公开(公告)日：2019-04-23

申请号：US15942230

申请日：2018-03-30

Applicant: APPLE INC.

Inventor： Karan Sanghi ,  Saurabh Garg ,  Haining Zhang

IPC: G06F13/10 ,  G06F1/3293 ,  G06F1/3287 ,  G06F13/42 ,  G06F9/4401 ,  G06F11/14 ,  G06F1/3228 ,  G06F1/3234

Abstract: Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a “shared” memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling.

公开(公告)号：US10042794B2

公开(公告)日：2018-08-07

申请号：US15011291

申请日：2016-01-29

Applicant: APPLE INC.

Inventor： Karan Sanghi ,  Vladislav Petkov ,  Radha Kumar Pulyala ,  Saurabh Garg ,  Haining Zhang

IPC: G06F13/28 ,  G06F13/40

Abstract: Methods and apparatus for a synchronized multi-directional transfer on an inter-processor communication (IPC) link. In one embodiment, the synchronized multi-directional transfer utilizes one or more buffers which are configured to accumulate data during a first state. The one or more buffers are further configured to transfer the accumulated data during a second state. Data is accumulated during a low power state where one or more processors are inactive, and the data transfer occurs during an operational state where the processors are active. Additionally, in some variants, the data transfer may be performed for currently available transfer resources, and halted until additional transfer resources are made available. In still other variants, one or more of the independently operable processors may execute traffic monitoring processes so as to optimize data throughput of the IPC link.

公开(公告)号：US09842036B2

公开(公告)日：2017-12-12

申请号：US14870923

申请日：2015-09-30

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Saurabh Garg ,  Vladislav Petkov ,  Haining Zhang

IPC: G06F11/00 ,  G06F11/20 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F11/2028 ,  G06F13/4022 ,  G06F13/4221 ,  G06F2201/805

Abstract: Methods and apparatus for controlled recovery of error information between two (or more) independently operable processors. The present disclosure provides solutions that preserve error information in the event of a fatal error, coordinate reset conditions between independently operable processors, and implement consistent frameworks for error information recovery across a range of potential fatal errors. In one exemplary embodiment, an applications processor (AP) and baseband processor (BB) implement an abort handler and power down handler sequence which enables error recovery over a wide range of crash scenarios. In one variant, assertion of signals between the AP and the BB enables the AP to reset the BB only after error recovery procedures have successfully completed.

公开(公告)号：US09798377B2

公开(公告)日：2017-10-24

申请号：US14879030

申请日：2015-10-08

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Saurabh Garg ,  Haining Zhang

IPC: G06F11/00 ,  G06F1/32 ,  G06F13/42 ,  G06F9/44 ,  G06F11/14

CPC classification number: G06F1/3293 ,  G06F1/3228 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F11/1417 ,  G06F11/1471 ,  G06F11/1474 ,  G06F13/4282 ,  G06F2201/805 ,  G06F2201/87 ,  Y02D10/122 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/152 ,  Y02D10/171

Abstract: Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a “shared” memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling.

公开(公告)号：US20170286322A1

公开(公告)日：2017-10-05

申请号：US15271102

申请日：2016-09-20

Applicant: Apple Inc.

Inventor： Saurabh Garg ,  Karan Sanghi ,  Vladislav Petkov ,  Haining Zhang

IPC: G06F12/14 ,  G06F21/62

CPC classification number: G06F12/1441 ,  G06F12/1081 ,  G06F2212/1052

Abstract: Methods and apparatus for registering and handling access violations of host memory. In one embodiment, a peripheral processor receives one or more window registers defining an extent of address space accessible from a host processor; responsive to an attempt to access an extent of address space outside of the extent of accessible address space, generates an error message; stores the error message within a violation register; and resumes operation of the peripheral processor upon clearance of the stored error message.