公开(公告)号：US20220208265A1

公开(公告)日：2022-06-30

申请号：US17139059

申请日：2020-12-31

Applicant: Arm Limited

Inventor： Fernando Garcia Redondo ,  Mudit Bhargava ,  Pranay Prabhat ,  Supreet Jeloka

IPC: G11C13/00 ,  G11C11/16

Abstract: An integrated circuit includes a primary memory array with cells switchable between first and second states. The circuit also includes sacrificial memory cells; each fabricated to be switchable between the first and second states and associated with at least one row of the primary array. A controller is configured to detect a write operation to a row of the primary array, stress a sacrificial cell associated with the row and detect a failure of the associated sacrificial cell. The sacrificial cells are fabricated to have lower write-cycle endurance than cells of the primary array or are subjected to more stress. Failure of a row of the primary array is predicted based, at least in part, on a detected failure of the associated sacrificial cell.

公开(公告)号：US10903822B2

公开(公告)日：2021-01-26

申请号：US16293518

申请日：2019-03-05

Applicant: Arm Limited

Inventor： Philex Ming-Yan Fan ,  Parameshwarappa Anand Kumar Savanth ,  Benoit Labbe ,  Bal S. Sandhu ,  Pranay Prabhat ,  James Edward Myers

IPC: H03K3/0231 ,  H02M3/07 ,  H03K19/20

Abstract: Various implementations described herein refer to an integrated circuit having a first stage and a second stage. The first stage has a step-down converter coupled to an oscillator between a first voltage supply and a second voltage supply. The second stage is coupled to the first stage, and the second stage has a current bias generator coupled to a diode-connected transistor between the first voltage supply and the second voltage supply. The second stage provides an intermediate voltage to the first stage.

公开(公告)号：US10896707B2

公开(公告)日：2021-01-19

申请号：US16290822

申请日：2019-03-01

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Rahul Mathur ,  Cyrille Nicolas Dray ,  Yann Sarrazin ,  Julien Vincent Poitrat ,  Yannis Jallamion-Grive ,  Pranay Prabhat ,  James Edward Myers ,  Graham Peter Knight ,  Jonas {hacek over (S)}vedas

IPC: G11C8/00 ,  G11C11/00 ,  G11C11/16

Abstract: Briefly, embodiments of claimed subject matter relate to adjusting, such as extending, a clock signal to permit completion of a write operations to a first memory type and/or to permit completion of read operations from a second memory type, wherein the first memory type and the second memory type are dissimilar from each other. In certain embodiments, the first memory type may comprise a magnetic random-access memory (MRAM) cell array, and the second memory type may comprise a static random-access memory (SRAM) cell array.

公开(公告)号：US20200287524A1

公开(公告)日：2020-09-10

申请号：US16293518

申请日：2019-03-05

Applicant: Arm Limited

Inventor： Philex Ming-Yan Fan ,  Parameshwarappa Anand Kumar Savanth ,  Benoit Labbe ,  Bal S. Sandhu ,  Pranay Prabhat ,  James Edward Myers

IPC: H03K3/0231 ,  H02M3/07

Abstract: Various implementations described herein refer to an integrated circuit having a first stage and a second stage. The first stage has a step-down converter coupled to an oscillator between a first voltage supply and a second voltage supply. The second stage is coupled to the first stage, and the second stage has a current bias generator coupled to a diode-connected transistor between the first voltage supply and the second voltage supply. The second stage provides an intermediate voltage to the first stage.

公开(公告)号：US20200066358A1

公开(公告)日：2020-02-27

申请号：US16107707

申请日：2018-08-21

Applicant: Arm Limited

Inventor： Supreet Jeloka ,  Pranay Prabhat ,  James Edward Myers

IPC: G11C16/28 ,  G11C11/4091 ,  G11C8/16 ,  G11C5/06 ,  G11C7/12 ,  G11C8/08 ,  G11C7/18 ,  G11C8/14

Abstract: Various implementations described herein refer to an integrated circuit having a memory structure with an array of bitcells accessible via wordlines arranged in rows and bitlines arranged in columns. The integrated circuit may include source lines coupled to the bitcells. The integrated circuit may include source line drivers coupled between the wordlines and the source lines, and the source line drivers may allow the source lines to be used as switched source lines.

公开(公告)号：US20180219549A1

公开(公告)日：2018-08-02

申请号：US15418331

申请日：2017-01-27

Applicant: ARM Limited

Inventor： Pranay Prabhat ,  Parameshwarappa Anand Kumar Savanth ,  James Edward Myers

IPC: H03K17/687

CPC classification number: H03K17/6872 ,  H01L29/1087 ,  H03K17/04163 ,  H03K19/00 ,  H03K19/0013 ,  H03K2217/0018 ,  H03K2217/0036

Abstract: Embodiments are described for digital forward body biasing CMOS circuits. In an embodiment, a power management unit limits the amount of time for which digital forward body biasing may be implemented. In another embodiment, once a CMOS circuit is put into a full digital forward body bias mode, the CMOS circuit is gradually brought back to a zero forward body bias mode. In another embodiment, charge is shared among biased transistor wells during transition intervals when transitioning from one bias mode to another.

公开(公告)号：US12002533B2

公开(公告)日：2024-06-04

申请号：US17814418

申请日：2022-07-22

Applicant: Arm Limited

Inventor： Pranay Prabhat ,  Mudit Bhargava ,  Fernando Garcia Redondo

IPC: G11C29/40 ,  G11C29/44

CPC classification number: G11C29/44

Abstract: Briefly, embodiments, such as methods and/or systems for operations and/or procedures to test magnetic memory devices. In a particular implementation, a bit error rate of a magnetic memory device may be estimated based, at least in part, on an observed bit error rate in the presence of an externally applied magnetic field.

公开(公告)号：US20230006467A1

公开(公告)日：2023-01-05

申请号：US17364057

申请日：2021-06-30

Applicant: Arm Limited

Inventor： Philex Ming-Yan Fan ,  Parameshwarappa Anand Kumar Savanth ,  Sahan Sajeewa Hiniduma Udugama Gamage ,  Pranay Prabhat ,  Benoit Labbe ,  Thanusree Achuthan

IPC: H02J50/00 ,  H02J50/20 ,  H02J50/40 ,  H02M3/07

Abstract: Subject matter disclosed herein may relate to detecting wireless signals and/or signal packets and may relate more particularly to detecting wireless signals and/or signal packets at energy-harvesting devices.

公开(公告)号：US20230003795A1

公开(公告)日：2023-01-05

申请号：US17363809

申请日：2021-06-30

Applicant: Arm Limited

Inventor： Fernando Garcia Redondo ,  James Edward Myers ,  Parameshwarappa Anand Kumar Savanth ,  Pranay Prabhat ,  Gary Dale Carpenter

IPC: G01R31/317 ,  G06F9/4401

Abstract: Subject matter disclosed herein may relate to wireless energy harvesting devices and may relate more particularly to system-on-a-chip testing for wireless energy harvesting devices.

公开(公告)号：US20220172762A1

公开(公告)日：2022-06-02

申请号：US17107725

申请日：2020-11-30

Applicant: Arm Limited

Inventor： Supreet Jeloka ,  Mudit Bhargava ,  Pranay Prabhat ,  Femando Garcia Redondo

IPC: G11C11/16

Abstract: Various implementations described herein are related to a method. The method may apply a write control voltage to a bitcell. The method may gradually ramp the write control voltage to the bitcell. The method may terminate application of the write control voltage to the bitcell when a write operation is sensed in the bitcell.