公开(公告)号：US11211111B1

公开(公告)日：2021-12-28

申请号：US17038795

申请日：2020-09-30

Applicant: Arm Limited

Inventor： Rahul Mathur ,  Mudit Bhargava ,  Supreet Jeloka ,  Andy Wangkun Chen

IPC: G11C11/40 ,  G11C11/4076 ,  G11C11/4094 ,  G11C5/02 ,  G11C15/04 ,  G11C11/4097

Abstract: A content-addressable memory (CAM) storage element includes bit storage cell bit comparison cells. The bit storage cell is arranged on a first die tier and includes at least one transistor, one or two bit lines, and a storage node. The bit comparison cell is arranged on a second die tier and has a match line, complementary search lines, and at least three transistors. The complementary search lines are decoupled from the bit line(s). A 3D connection couples the storage node to one of the transistors of the second die tier. The CAM cell performs at least one CAM search per clock cycle using at least four transistors per search, including the at least one transistor of the bit storage cell and the at least three transistors of the bit comparison cell, and to output results of the at least one CAM search on the match line.

公开(公告)号：US20210082496A1

公开(公告)日：2021-03-18

申请号：US17107559

申请日：2020-11-30

Applicant: Arm Limited

Inventor： Rahul Mathur ,  Vivek Asthana ,  Ankur Garcia Goel ,  Nikhil Kaushik ,  Rachit Ahuja ,  Bikas Maiti ,  Yew Keong Chong

IPC: G11C11/419 ,  G11C11/418

Abstract: Various implementations described herein are directed to an integrated circuit having a wordline driver coupled to a bitcell via a wordline. The integrated circuit may include a read assist transistor coupled to the wordline between the wordline driver and the bitcell. While activated, the read assist transistor may generate an adaptive underdrive on the wordline, the level of which depends on the process, temperature and voltage of operation of the memory, when the wordline is selected and driven by the wordline driver.

公开(公告)号：US20190066772A1

公开(公告)日：2019-02-28

申请号：US15691001

申请日：2017-08-30

Applicant: ARM Limited

Inventor： Abhairaj Singh ,  Vivek Asthana ,  Monu Rathore ,  Ankur Goel ,  Nikhil Kaushik ,  Rachit Ahuja ,  Rahul Mathur ,  Bikas Maiti ,  Yew Keong Chong

IPC: G11C11/419

Abstract: Various implementations described herein are directed to an integrated circuit having a wordline driver coupled to a bitcell via a wordline. The integrated circuit may include a read assist transistor coupled to the wordline between the wordline driver and the bitcell. While activated, the read assist transistor may generate an adaptive underdrive on the wordline, the level of which depends on the process, temperature and voltage of operation of the memory, when the wordline is selected and driven by the wordline driver.

公开(公告)号：US12087353B2

公开(公告)日：2024-09-10

申请号：US17885709

申请日：2022-08-11

Applicant: Arm Limited

Inventor： Edward Martin McCombs, Jr. ,  Andrew David Tune ,  Sean James Salisbury ,  Rahul Mathur ,  Hsin-Yu Chen ,  Phani Raja Bhushan Chalasani

IPC: G11C11/00 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096

CPC classification number: G11C11/4096 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4094

Abstract: A burst read with flexible burst length for on-chip memory, such as, for example, system cache memory, hierarchical cache memory, system memory, etc. is provided. Advantageously, successive burst reads are performed with less signal toggling and fewer bitline swings.

公开(公告)号：US20240038297A1

公开(公告)日：2024-02-01

申请号：US17874611

申请日：2022-07-27

Applicant: Arm Limited

Inventor： Rahul Mathur ,  Mudit Bhargava

IPC: G11C11/419 ,  G11C11/412 ,  H01L27/11

CPC classification number: G11C11/419 ,  G11C11/412 ,  H01L27/1104

Abstract: Various implementations described herein are related to a device having bitline drivers coupled to passgates of bitcells via bitlines and buried metal lines formed within a substrate including a buried enable signal line and a buried ground line coupled to ground connections of the bitline drivers. The buried enable signal line transfers a negative bias to a selected bitline of the bitlines via the buried ground line that is coupled to the ground connections of the bitline drivers so as to increase gate-source bias of the passgates of the selected bitcell to thereby enhance write capability of the selected bitcell.

公开(公告)号：US20230354571A1

公开(公告)日：2023-11-02

申请号：US18012917

申请日：2021-06-23

Applicant: Arm Limited

Inventor： Rahul Mathur ,  Mudit Bhargava ,  Saurabh Pijuskumar Sinha ,  Brian Tracy Cline ,  Yew Keong Chong

IPC: H10B10/00

CPC classification number: H10B10/12

Abstract: Various implementations described herein refer to a device having a memory structure with a substrate. The device may have a signal wire buried or partially buried within at least one of the substrate and a dielectric for transmitting electrical signals. The device may be manufactured as a memory device having a memory cell structure with the signal wire buried or partially buried in the substrate.

公开(公告)号：US20230178538A1

公开(公告)日：2023-06-08

申请号：US18103313

申请日：2023-01-30

Applicant: Arm Limited

Inventor： Rahul Mathur ,  Xiaoqing Xu ,  Andy Wangkun Chen ,  Mudit Bhargava ,  Brian Tracy Cline ,  Saurabh Pijuskumar Sinha

IPC: H01L27/02 ,  G06F30/31 ,  H01L21/768 ,  H01L23/535 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L27/0207 ,  G06F30/31 ,  H01L21/76898 ,  H01L23/535 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06544

Abstract: According to one implementation of the present disclosure, a method includes fabricating a memory macro unit; forming a through silicon via (TSV); and bonding the TSV at least partially through the fabricated memory macro unit. According to one implementation of the present disclosure, a computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to perform operations including: receiving a user input corresponding to dimensions of respective pitches of one or more through silicon vias (TSVs); determining whether dimensions of a memory macro unit is greater than a size threshold, wherein the size threshold corresponds to the received user input; and determining one or more through silicon via (TSV) positionings based on the determined dimensions of the memory macro unit.

公开(公告)号：US11532353B2

公开(公告)日：2022-12-20

申请号：US17162532

申请日：2021-01-29

Applicant: Arm Limited

Inventor： Mudit Bhargava ,  Rahul Mathur ,  Andy Wangkun Chen

IPC: G11C11/41 ,  G11C11/419 ,  G11C11/418

Abstract: According to one implementation of the present disclosure, an integrated circuit comprises a memory macro unit that includes an input/output (I/O) circuit block, where read/write circuitry of the I/O circuit block is apportioned on at least first and second tiers of the memory macro unit. In a particular implementation, read circuitry of the read/write circuitry is arranged on the first tier and write circuitry of the read/write circuitry is arranged on the second tier.

公开(公告)号：US20220391469A1

公开(公告)日：2022-12-08

申请号：US17339895

申请日：2021-06-04

Applicant: Arm Limited

Inventor： Supreet Jeloka ,  Mudit Bhargava ,  Saurabh Pijuskumar Sinha ,  Rahul Mathur

IPC: G06F17/16 ,  G06F9/30

Abstract: According to one implementation of the present disclosure, a method includes performing a spatial alignment of at least one of first or second data tiers of a circuit; and performing a computation based on the spatial alignment of the at least one of the first and second data tiers. According to another implementation of the present disclosure, a circuit includes: a compute circuitry; and at least first and second data tiers of two or more data tiers positioned at least partially overlapping one another. In an example, each of the at least first and second data tiers is coupled to the compute circuitry. In certain implementations, the positioning of the first and second data tiers at least partially overlapping one another corresponds to a spatial alignment.

公开(公告)号：US11475944B2

公开(公告)日：2022-10-18

申请号：US17107559

申请日：2020-11-30

Applicant: Arm Limited

Inventor： Rahul Mathur ,  Vivek Asthana ,  Ankur Garcia Goel ,  Nikhil Kaushik ,  Rachit Ahuja ,  Bikas Maiti ,  Yew Keong Chong

IPC: G11C11/419 ,  G11C11/418

Abstract: Various implementations described herein are directed to an integrated circuit having a wordline driver coupled to a bitcell via a wordline. The integrated circuit may include a read assist transistor coupled to the wordline between the wordline driver and the bitcell. While activated, the read assist transistor may generate an adaptive underdrive on the wordline, the level of which depends on the process, temperature and voltage of operation of the memory, when the wordline is selected and driven by the wordline driver.