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    Management of caches
    21.
    发明申请
    Management of caches 有权
    管理缓存

    公开(公告)号：US20150039833A1

    公开(公告)日：2015-02-05

    申请号：US13957105

    申请日：2013-08-01

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Kai K. Chang ,  Yasuko Eckert ,  Gabriel H. Loh ,  Lisa R. Hsu

    IPC: G06F12/08 ,  G06F12/12

    CPC classification number: G06F12/0848 ,  G06F12/122 ,  Y02D10/13

    Abstract: A system and method for efficiently powering down banks in a cache memory for reducing power consumption. A computing system includes a cache array and a corresponding cache controller. The cache array includes multiple banks, each comprising multiple cache sets. In response to a request to power down a first bank of the multiple banks in the cache array, the cache controller selects a cache line of a given type in the first bank and determines whether a respective locality of reference for the selected cache line exceeds a threshold. If the threshold is exceeded, then the selected cache line is migrated to a second bank in the cache array. If the threshold is not exceeded, then the selected cache line is written back to lower-level memory.

    Abstract translation: 一种用于在高速缓冲存储器中有效地降低存储器的电力以降低功耗的系统和方法。 计算系统包括高速缓存阵列和对应的高速缓存控制器。 高速缓存阵列包括多个存储体，每个存储体包括多个缓存集。 响应于对高速缓存阵列中的多个存储体的第一存储体断电的请求，高速缓存控制器在第一存储体中选择给定类型的高速缓存行，并且确定所选高速缓存行的各个参考位置是否超过 阈。 如果超过阈值，则将所选择的高速缓存行迁移到高速缓存阵列中的第二组。 如果不超过阈值，则将所选的高速缓存行写回低级存储器。

    Computation Memory Operations in a Logic Layer of a Stacked Memory
    22.
    发明申请
    Computation Memory Operations in a Logic Layer of a Stacked Memory 有权
    堆叠存储器逻辑层中的计算存储器操作

    公开(公告)号：US20140181483A1

    公开(公告)日：2014-06-26

    申请号：US13724506

    申请日：2012-12-21

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： James M. O'CONNOR ,  Nuwan S. Jayasena ,  Gabriel H. Loh ,  Michael Ignatowski ,  Michael J. Schulte

    IPC: G06F9/30

    CPC classification number: G06F15/7821 ,  Y02D10/12 ,  Y02D10/13

    Abstract: Some die-stacked memories will contain a logic layer in addition to one or more layers of DRAM (or other memory technology). This logic layer may be a discrete logic die or logic on a silicon interposer associated with a stack of memory dies. Additional circuitry/functionality is placed on the logic layer to implement functionality to perform various computation operations. This functionality would be desired where performing the operations locally near the memory devices would allow increased performance and/or power efficiency by avoiding transmission of data across the interface to the host processor.

    Abstract translation: 除了一层或多层DRAM（或其他存储器技术）之外，一些堆叠堆叠的存储器将包含逻辑层。 该逻辑层可以是与存储器管芯堆叠相关联的硅插入器上的离散逻辑管芯或逻辑。 额外的电路/功能被放置在逻辑层上以实现执行各种计算操作的功能。 通过避免通过接口向主机处理器传输数据，执行本地在存储器件附近的操作将允许提高性能和/或功率效率将需要该功能。

    Compound Memory Operations in a Logic Layer of a Stacked Memory
    23.
    发明申请
    Compound Memory Operations in a Logic Layer of a Stacked Memory 审中-公开
    堆叠存储器的逻辑层中的复合存储器操作

    公开(公告)号：US20140181427A1

    公开(公告)日：2014-06-26

    申请号：US13724338

    申请日：2012-12-21

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Nuwan S. JAYASENA ,  James M. O'Connor ,  Gabriel H. Loh ,  Michael J. Schulte ,  Bradford M. Beckmann ,  Michael Ignatowski

    IPC: G06F12/00

    CPC classification number: G06F9/3004 ,  G06F9/3455 ,  G06F15/7821

    Abstract: Some die-stacked memories will contain a logic layer in addition to one or more layers of DRAM (or other memory technology). This logic layer may be a discrete logic die or logic on a silicon interposer associated with a stack of memory dies. Additional circuitry/functionality is placed on the logic layer to implement functionality to perform various data movement and address calculation operations. This functionality would allow compound memory operations—a single request communicated to the memory that characterizes the accesses and movement of many data items. This eliminates the performance and power overheads associated with communicating address and control information on a fine-grain, per-data-item basis from a host processor (or other device) to the memory. This approach also provides better visibility of macro-level memory access patterns to the memory system and may enable additional optimizations in scheduling memory accesses.

    Abstract translation: 除了一层或多层DRAM（或其他存储器技术）之外，一些堆叠堆叠的存储器将包含逻辑层。 该逻辑层可以是与存储器管芯堆叠相关联的硅插入器上的离散逻辑管芯或逻辑。 额外的电路/功能被放置在逻辑层上以实现执行各种数据移动和地址计算操作的功能。 该功能将允许复合存储器操作 - 传达到存储器的单个请求，其表征许多数据项的访问和移动。 这消除了与从主处理器（或其他设备）到存储器的以细粒度，每数据项为基础传送地址和控制信息相关联的性能和功耗开销。 这种方法还提供了对存储器系统的宏级存储器访问模式的更好的可见性，并且可以在调度存储器访问中实现附加优化。

    PROCESSING ENGINE FOR COMPLEX ATOMIC OPERATIONS
    24.
    发明申请
    PROCESSING ENGINE FOR COMPLEX ATOMIC OPERATIONS 有权
    加工发动机用于复杂的原子操作

    公开(公告)号：US20140181421A1

    公开(公告)日：2014-06-26

    申请号：US13725724

    申请日：2012-12-21

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： James M. O'CONNOR ,  Michael J. Schulte ,  Nuwan S. Jayasena ,  Gabriel H. Loh

    IPC: G06F12/08

    CPC classification number: G06F9/50 ,  G06F9/526 ,  G06F2209/521 ,  G06F2209/522

    Abstract: A system includes an atomic processing engine (APE) coupled to an interconnect. The interconnect is to couple to one or more processor cores. The APE receives a plurality of commands from the one or more processor cores through the interconnect. In response to a first command, the APE performs a first plurality of operations associated with the first command. The first plurality of operations references multiple memory locations, at least one of which is shared between two or more threads executed by the one or more processor cores.

    Abstract translation: 系统包括耦合到互连的原子处理引擎（APE）。 互连将耦合到一个或多个处理器内核。 APE通过互连从一个或多个处理器核接收多个命令。 响应于第一命令，APE执行与第一命令相关联的第一多个操作。 第一组多个操作引用多个存储器位置，其中至少一个在一个或多个处理器核心执行的两个或多个线程之间共享。

    MECHANISMS TO BOUND THE PRESENCE OF CACHE BLOCKS WITH SPECIFIC PROPERTIES IN CACHES
    25.
    发明申请
    MECHANISMS TO BOUND THE PRESENCE OF CACHE BLOCKS WITH SPECIFIC PROPERTIES IN CACHES 有权
    在缓存中具有特定属性的高速缓存块的存在机制

    公开(公告)号：US20140181412A1

    公开(公告)日：2014-06-26

    申请号：US13725011

    申请日：2012-12-21

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Mithuna S. Thottethodi ,  Gabriel H. Loh ,  James M. O'Connor ,  Yasuko Eckert ,  Bradford M. Beckmann

    IPC: G06F12/08

    CPC classification number: G06F12/0871 ,  G06F12/0848

    Abstract: A system and method for efficiently limiting storage space for data with particular properties in a cache memory. A computing system includes a cache and one or more sources for memory requests. In response to receiving a request to allocate data of a first type, a cache controller allocates the data in the cache responsive to determining a limit of an amount of data of the first type permitted in the cache is not reached. The controller maintains an amount and location information of the data of the first type stored in the cache. Additionally, the cache may be partitioned with each partition designated for storing data of a given type. Allocation of data of the first type is dependent at least upon the availability of a first partition and a limit of an amount of data of the first type in a second partition.

    Abstract translation: 一种用于有效地限制高速缓冲存储器中具有特定属性的数据的存储空间的系统和方法。 计算系统包括缓存和用于存储器请求的一个或多个源。 响应于接收到分配第一类型的数据的请求，高速缓存控制器响应于确定未达到高速缓存中允许的第一类型的数据量的极限而分配缓存中的数据。 控制器维护存储在高速缓存中的第一类型的数据的量和位置信息。 此外，可以用指定用于存储给定类型的数据的每个分区对高速缓存进行分区。 第一类型的数据的分配至少依赖于第一分区的可用性和第二分区中第一类型的数据量的限制。

    LARGE NUMBER INTEGER ADDITION USING VECTOR ACCUMULATION
    28.
    发明公开
    LARGE NUMBER INTEGER ADDITION USING VECTOR ACCUMULATION 审中-公开

    公开(公告)号：US20240319964A1

    公开(公告)日：2024-09-26

    申请号：US18126107

    申请日：2023-03-24

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Onur Kayiran ,  Lee Evan Eisen ,  Michael Estlick ,  Jay Fleischman ,  Matthew R. Poremba ,  Gabriel H. Loh

    IPC: G06F7/503

    CPC classification number: G06F7/503

    Abstract: A processor includes one or more processor cores configured to perform accumulate top (ACCT) and accumulate bottom (ACCB) instructions. To perform such instructions, at least one processor core of the processor includes an ACCT data path that adds a first portion of a block of data to a first lane of a set of lanes of a top accumulator and adds a carry-out bit to a second lane of the set of lanes of the top accumulator. Further, the at least one processor core includes an ACCB data path that adds a second portion of the block of data to a first lane of a set of lanes of a bottom accumulator and adds a carry-out bit to a second lane of the set of lanes of the bottom accumulator.

    BIGNUM ADDITION AND/OR SUBTRACTION WITH CARRY PROPAGATION
    29.
    发明公开
    BIGNUM ADDITION AND/OR SUBTRACTION WITH CARRY PROPAGATION 审中-公开

    公开(公告)号：US20240111489A1

    公开(公告)日：2024-04-04

    申请号：US17955634

    申请日：2022-09-29

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Onur Kayiran ,  Michael Estlick ,  Masab Ahmad ,  Gabriel H. Loh

    IPC: G06F7/498 ,  G06F7/506

    CPC classification number: G06F7/4981 ,  G06F7/506

    Abstract: A processing unit includes a plurality of adders and a plurality of carry bit generation circuits. The plurality of adders add first and second X bit binary portion values of a first Y bit binary value and a second Y bit binary value. Y is a multiple of X. The plurality of adders further generate first carry bits. The plurality of carry bit generation circuits is coupled to the plurality of adders, respectively, and receive the first carry bits. The plurality of carry bit generation circuits generate second carry bits based on the first carry bits. The plurality of adders use the second carry bits to add the first and second X bit binary portions of the first and second Y bit binary values, respectively.

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