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    Self-adjusting clock doubler and integrated circuit clock distribution system using same
    5.
    发明授权
    Self-adjusting clock doubler and integrated circuit clock distribution system using same 有权
    自调整时钟倍增器和集成电路时钟分配系统使用相同

    公开(公告)号：US09319037B2

    公开(公告)日：2016-04-19

    申请号：US14171469

    申请日：2014-02-03

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Arun Sundaresan Iyer ,  Alok Baluni ,  Samuel Naffziger ,  Sriram Sambamurthy

    IPC: H03B19/00 ,  H03K5/13 ,  H03K5/00

    CPC classification number: H03K5/131 ,  H03K2005/00058

    Abstract: In one form, a clock doubler includes a switched inverter, an exclusive logic circuit, and a control signal generation circuit. The switched inverter has first and second control inputs for respectively receiving first and second control signals, a signal input for receiving a clock input signal, and an output. The exclusive logic circuit has a first input for receiving the clock input signal, a second input coupled to the output of the switched inverter, and an output for providing a clock output signal. A control signal generation circuit provides the first and second control signals in response to the clock output signal. The clock doubler may be used in a clock distribution circuit for an integrated circuit that also includes a phase locked loop for providing the input clock signals, and a plurality of clock sub-domains each having one of the clock doublers.

    Abstract translation: 在一种形式中，时钟倍频器包括开关逆变器，专用逻辑电路和控制信号发生电路。 开关逆变器具有用于分别接收第一和第二控制信号的第一和第二控制输入，用于接收时钟输入信号的信号输入和输出。 专用逻辑电路具有用于接收时钟输入信号的第一输入端，耦合到开关逆变器的输出端的第二输入端和用于提供时钟输出信号的输出端。 控制信号产生电路响应于时钟输出信号提供第一和第二控制信号。 时钟倍频器可以用于还包括用于提供输入时钟信号的锁相环的集成电路的时钟分配电路，以及每个具有时钟倍增器之一的多个时钟子域。

    SELF-ADJUSTING CLOCK DOUBLER AND INTEGRATED CIRCUIT CLOCK DISTRIBUTION SYSTEM USING SAME
    6.
    发明申请
    SELF-ADJUSTING CLOCK DOUBLER AND INTEGRATED CIRCUIT CLOCK DISTRIBUTION SYSTEM USING SAME 有权
    自调整时钟双工器和集成电路时钟分配系统

    公开(公告)号：US20150222277A1

    公开(公告)日：2015-08-06

    申请号：US14171469

    申请日：2014-02-03

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Arun Sundaresan Iyer ,  Alok Baluni ,  Samuel Naffziger ,  Sriram Sambamurthy

    IPC: H03L7/081 ,  H03K5/13

    CPC classification number: H03K5/131 ,  H03K2005/00058

    Abstract: In one form, a clock doubler includes a switched inverter, an exclusive logic circuit, and a control signal generation circuit. The switched inverter has first and second control inputs for respectively receiving first and second control signals, a signal input for receiving a clock input signal, and an output. The exclusive logic circuit has a first input for receiving the clock input signal, a second input coupled to the output of the switched inverter, and an output for providing a clock output signal. A control signal generation circuit provides the first and second control signals in response to the clock output signal. The clock doubler may be used in a clock distribution circuit for an integrated circuit that also includes a phase locked loop for providing the input clock signals, and a plurality of clock sub-domains each having one of the clock doublers.

    Abstract translation: 在一种形式中，时钟倍频器包括开关逆变器，专用逻辑电路和控制信号发生电路。 开关逆变器具有用于分别接收第一和第二控制信号的第一和第二控制输入，用于接收时钟输入信号的信号输入和输出。 专用逻辑电路具有用于接收时钟输入信号的第一输入端，耦合到开关逆变器的输出端的第二输入端和用于提供时钟输出信号的输出端。 控制信号产生电路响应于时钟输出信号提供第一和第二控制信号。 时钟倍频器可以用于还包括用于提供输入时钟信号的锁相环的集成电路的时钟分配电路，以及每个具有时钟倍增器之一的多个时钟子域。

    Mission mode Vmin prediction and calibration
    9.
    发明授权
    Mission mode Vmin prediction and calibration 有权

    公开(公告)号：US11462294B2

    公开(公告)日：2022-10-04

    申请号：US17121110

    申请日：2020-12-14

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Ashish Jain ,  Sriram Sundaram ,  Samuel Naffziger

    IPC: G11C7/10 ,  G11C29/50 ,  G11C7/22 ,  H03K3/03

    Abstract: The low end operating voltage of an integrated circuit is adjusted. Oscillations are counted at a ring oscillator on the integrated circuit over a designated period of clock cycles. Based on the number of oscillations, a prediction model associated with a first set of device degradation data and a second set of static random-access memory (SRAM) low end operating voltage data is used to select a low end operating voltage limit for a processor on the integrated circuit. The low end operating voltage of the processor is set based on the selected low end operating voltage limit. These steps are repeated multiple times during operation of the processor. A method of testing integrated circuits to provide the data employed to produce the prediction model is also provided.

    Swizzling in 3D stacked memory
    10.
    发明授权
    Swizzling in 3D stacked memory 有权

    公开(公告)号：US10303398B2

    公开(公告)日：2019-05-28

    申请号：US15794457

    申请日：2017-10-26

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： John Wuu ,  Michael K. Ciraula ,  Russell Schreiber ,  Samuel Naffziger

    IPC: G11C5/06 ,  G06F3/06 ,  G06F12/1009

    Abstract: A processing system includes a compute die and a stacked memory stacked with the compute die. The stacked memory includes a first memory die and a second memory die stacked on top of the first memory die. A parallel access using a single memory address is directed towards different memory banks of the first memory die and the second memory die. The single memory address of the parallel access is swizzled to access the first memory die and the second memory die at different physical locations.

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