公开(公告)号：US20240321702A1

公开(公告)日：2024-09-26

申请号：US18474166

申请日：2023-09-25

申请人： Advanced Micro Devices, Inc. ,  Xilinx, Inc.

发明人： Yan Wang ,  Kevin Gillespie ,  Samuel Naffziger ,  Richard Schultz ,  Raja Swaminathan ,  Omar Zia ,  John Wuu

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L23/367 ,  H01L25/065

CPC分类号： H01L23/49822 ,  H01L23/3675 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/32 ,  H01L25/0652 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/32146 ,  H01L2224/32165 ,  H01L2924/1431 ,  H01L2924/1437 ,  H01L2924/351

摘要： A method for providing backside power can include providing a first circuit die having a first metal stack. The method can also include connecting a second metal stack of a second circuit die to the first metal stack of the first circuit die, wherein a backside power delivery network is located in a passivation layer of at least one of the first circuit die or the second circuit die. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20240321827A1

公开(公告)日：2024-09-26

申请号：US18474158

申请日：2023-09-25

申请人： Advanced Micro Devices, Inc. ,  Xilinx, Inc.

发明人： Omar Zia ,  Thomas D Burd ,  Kevin Gillespie ,  Samuel Naffziger ,  Richard Schultz ,  Raja Swaminathan ,  Srividhya Venkataraman ,  Yan Wang ,  John Wuu

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/36 ,  H01L23/48 ,  H10B80/00

CPC分类号： H01L25/0657 ,  H01L23/36 ,  H01L23/481 ,  H01L24/08 ,  H01L24/16 ,  H01L24/80 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2224/16145 ,  H01L2224/80895 ,  H01L2224/80896

摘要： A method for circuit die stacking can include providing a first circuit die having a first metal stack, wherein the first circuit die corresponds to a primary thermal source of an integrated circuit including the first circuit die. The method can additionally include providing a second circuit die of the integrated circuit, wherein the second circuit die has a second metal stack and is configured for connection to at least one of a package substrate or an additional die. The method can also include connecting the first metal stack to the second metal stack. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20240321668A1

公开(公告)日：2024-09-26

申请号：US18474138

申请日：2023-09-25

申请人： Advanced Micro Devices, Inc. ,  Xilinx, Inc.

发明人： Thomas D. Burd ,  Gabriel H. Loh ,  John Wuu ,  Kevin Gillespie ,  Raja Swaminathan ,  Richard Schultz ,  Samuel Naffziger ,  Srividhya Venkataraman ,  Yan Wang

IPC分类号： H01L23/34 ,  H01L23/00 ,  H01L25/065 ,  H10B80/00

CPC分类号： H01L23/34 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/80 ,  H01L25/0652 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2224/16225 ,  H01L2224/32221 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1437

摘要： A method for die pair partitioning can include providing a first circuit die having a first metal stack. The method can additionally include positioning a second circuit die having a second metal stack in a manner that places a temperature sensor in a transistor layer of the second circuit die in planar proximity to at least one hot spot located in an additional transistor layer of the first circuit die. The method can also include connecting the first metal stack of the first circuit die to the second metal stack of the second circuit die. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US11650249B1

公开(公告)日：2023-05-16

申请号：US16941422

申请日：2020-07-28

申请人： XILINX, INC.

发明人： Yan Wang ,  Nui Chong

IPC分类号： G01R31/3185 ,  G01R31/28 ,  G01R3/00

CPC分类号： G01R31/318511 ,  G01R31/2884

摘要： Examples described herein generally relate to wafer testing and structures implemented on a wafer for wafer testing. In an example method for testing a wafer, power is applied to a first pad in a test site (TS) region on the wafer. The TS region is electrically connected to a device under test (DUT) region on the wafer. The DUT region includes a DUT. The TS region and DUT region are in a first and second scribe line, respectively, on the wafer. A third scribe line is disposed on the wafer between the TS region and the DUT region. A signal is detected from a second pad in the TS region on the wafer. The signal is at least in part a response of the DUT to the power applied to the first pad.

公开(公告)号：US11508667B1

公开(公告)日：2022-11-22

申请号：US16717708

申请日：2019-12-17

申请人： XILINX, INC.

发明人： James Karp ,  Yan Wang

IPC分类号： H01L23/552 ,  H01L23/528 ,  H01L23/50

摘要： Some examples described herein provide for a shield in an integrated circuit (IC) structure for memory protection. In an example, an IC structure includes a semiconductor material, an interconnect structure, and a shield. The semiconductor material has a protected region. Devices are disposed in a first side of the semiconductor material in the protected region. The interconnect structure is disposed on the first side of the semiconductor material. The interconnect structure interconnects the devices in the protected region. The shield is disposed on a second side of the semiconductor material opposite from the first side of the semiconductor material. The shield is positioned aligned with the protected region.

公开(公告)号：US11119146B1

公开(公告)日：2021-09-14

申请号：US16997630

申请日：2020-08-19

申请人： XILINX, INC.

发明人： Nui Chong ,  Yan Wang ,  Hui-Wen Lin

IPC分类号： G01R31/28 ,  H01L21/66

摘要： Examples described herein generally relate to testing of bonded wafers and structures implemented for such testing. In an example method, power is applied to a first pad on a stack of bonded wafers. A wafer of the stack includes a process control monitor (PCM) region that includes structure regions. Each structure region is a device under test region, dummy region, and/or chain interconnect region (CIR). The stack includes a serpentine chain test structure (SCTS) electrically connected between first and second metal features in the wafer in first and second CIRs, respectively, in the PCM region. The SCTS includes segments, one or more of which are disposed between neighboring structure regions in the PCM region that are not the first and second CIRs. A signal is detected from a second pad on the stack. The first and second pads are electrically connected to the first and second metal features, respectively.