公开(公告)号：US12249585B2

公开(公告)日：2025-03-11

申请号：US18582586

申请日：2024-02-20

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen Hung Huang

IPC: H01L23/66 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01Q1/22

Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes an antenna layer, a first circuit layer and a second circuit layer. The antenna layer has a first coefficient of thermal expansion (CTE). The first circuit layer is disposed over the antenna layer. The first circuit layer has a second CTE. The second circuit layer is disposed over the antenna layer. The second circuit layer has a third CTE. A difference between the first CTE and the second CTE is less than a difference between the first CTE and the third CTE.

公开(公告)号：US11961799B2

公开(公告)日：2024-04-16

申请号：US17204829

申请日：2021-03-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen Hung Huang

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/562

Abstract: A semiconductor substrate structure and a method of manufacturing a semiconductor substrate structure are provided. The semiconductor substrate structure includes a substrate, an electronic device, and a filling material. The substrate defines a cavity. The electronic device is disposed in the cavity and spaced apart from the substrate by a gap. The filling material is disposed in the gap and covers a first region of an upper surface of the electronic device.

公开(公告)号：US11848280B2

公开(公告)日：2023-12-19

申请号：US17105277

申请日：2020-11-25

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen Hung Huang ,  Yu-Ju Liao

IPC: H01L21/48 ,  H01L21/52 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/562 ,  H01L21/4846 ,  H01L21/4857 ,  H01L21/52 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49894

Abstract: An assembly structure and a method for manufacturing the same are provided. The method for manufacturing the assembly structure includes providing a substrate defining an active region and a side rail surrounding the active region; and forming a frame structure on the side rail.

公开(公告)号：US11791293B2

公开(公告)日：2023-10-17

申请号：US17480123

申请日：2021-09-20

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen Hung Huang ,  Yan Wen Chung ,  Wei Chu Sun

IPC: H01L29/40 ,  H01L23/48 ,  H01L23/52 ,  H01L23/66 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/66 ,  H01L23/49822 ,  H01L23/562 ,  H01L2223/6616 ,  H01L2223/6677

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes an antenna zone and a routing zone. The routing zone is disposed on the antenna zone, where the antenna zone includes a first insulation layer and two or more second insulation layer and a thickness of the first insulation layer is different from that of the second insulation layer.

公开(公告)号：US11728260B2

公开(公告)日：2023-08-15

申请号：US17125842

申请日：2020-12-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen Hung Huang

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/562 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/3511 ,  H01L2924/37001

Abstract: A wiring structure and a method for manufacturing the same are provided. The wiring structure includes a lower conductive structure, an upper conductive structure and a conductive via. The lower conductive structure includes a first dielectric layer and a first circuit layer in contact with the first dielectric layer. The upper conductive structure is attached to the lower conductive structure. The upper conductive structure includes a plurality of second dielectric layers, a plurality of second circuit layers in contact with the second dielectric layers, and defines an accommodating hole. An insulation material is disposed in the accommodating hole. The conductive via extends through the insulation material, and electrically connects the lower conductive structure.

公开(公告)号：US11721678B2

公开(公告)日：2023-08-08

申请号：US17330240

申请日：2021-05-25

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Mei Huang ,  Shih-Yu Wang ,  I-Ting Lin ,  Wen Hung Huang ,  Yuh-Shan Su ,  Chih-Cheng Lee ,  Hsing Kuo Tien

IPC: H01L25/16 ,  H01L23/31 ,  H01L23/00 ,  H01L23/522 ,  H01L21/56 ,  H01L23/528 ,  H01L23/29

CPC classification number: H01L25/16 ,  H01L21/563 ,  H01L23/315 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/17 ,  H01L23/293 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401

Abstract: A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.

公开(公告)号：US11721634B2

公开(公告)日：2023-08-08

申请号：US17157795

申请日：2021-01-25

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen Hung Huang

IPC: H01L23/31 ,  H01L23/49 ,  H01L23/13 ,  H01L23/52 ,  H01L23/538 ,  H01L21/48 ,  H01L21/52 ,  H01L21/56

CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/4857 ,  H01L21/52 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386

Abstract: A conductive structure includes a core portion, a plurality of electronic devices and a filling material. The core portion defines a cavity. The electronic devices are disposed in the cavity of the core portion. The filling material is disposed between the electronic devices and a sidewall of the cavity of the core portion.

公开(公告)号：US10978417B2

公开(公告)日：2021-04-13

申请号：US16398016

申请日：2019-04-29

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen Hung Huang

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L21/768

Abstract: A wiring structure includes an upper conductive structure, a lower conductive structure and an intermediate layer. The upper conductive structure includes at least one upper dielectric layer and at least one upper circuit layer in contact with the dielectric layer. The lower conductive structure includes at least one lower dielectric layer and at least one lower circuit layer in contact with the lower dielectric layer. The at least one lower dielectric layer of the lower conductive structure is substantially free of glass fiber. The intermediate layer is disposed between the upper conductive structure and the lower conductive structure and bonds the upper conductive structure and the lower conductive structure together. The upper conductive structure is electrically connected to the lower conductive structure.

公开(公告)号：US10903169B2

公开(公告)日：2021-01-26

申请号：US16399907

申请日：2019-04-30

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen Hung Huang

IPC: H01L23/538 ,  H01L23/31 ,  H01L21/48 ,  H01L21/52 ,  H01L21/56

Abstract: A conductive structure includes a core portion, a plurality of electronic devices and a filling material. The core portion defines a cavity. The electronic devices are disposed in the cavity of the core portion. The filling material is disposed between the electronic devices and a sidewall of the cavity of the core portion.

公开(公告)号：US10861780B1

公开(公告)日：2020-12-08

申请号：US16410872

申请日：2019-05-13

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen Hung Huang

IPC: H05K1/02 ,  H01L23/498 ,  H01L21/48 ,  H05K3/46 ,  H05K3/00 ,  H05K1/11

Abstract: A wiring structure includes an upper conductive structure, a lower conductive structure, a lower encapsulant and an intermediate layer. The upper conductive structure includes at least one upper dielectric layer and at least one upper circuit layer in contact with the upper dielectric layer. The lower conductive structure includes at least one lower dielectric layer and at least one lower circuit layer in contact with the lower dielectric layer. The lower encapsulant surrounds a lateral peripheral surface of the lower conductive structure. The intermediate layer is disposed between the upper conductive structure and the lower conductive structure to bond the upper conductive structure and the lower conductive structure together. The upper conductive structure is electrically connected to the lower conductive structure.