公开(公告)号：US20080219054A1

公开(公告)日：2008-09-11

申请号：US12039461

申请日：2008-02-28

申请人： Fumitaka ARAI ,  Masaru Kito ,  Mitsuru Sato

发明人： Fumitaka ARAI ,  Masaru Kito ,  Mitsuru Sato

IPC分类号： G11C11/34

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor memory device includes a plurality of active areas each extending in a first direction and including a memory cell string which includes select transistors and memory cells, current paths of which are connected in series, a first extension portion which is provided between one-side terminal end portions of two active areas neighboring in a second direction that crosses the first direction, and a second extension portion which is provided between other-side terminal end portions of the two active areas neighboring in the second direction, the first and second extension portions connecting the two active areas in a loop configuration.

摘要翻译： 半导体存储器件包括多个有源区，每个有源区各自沿第一方向延伸，并且包括存储单元串，该存储单元串包括选择晶体管和存储单元，其电流通路串联连接，第一延伸部分设置在一侧 在与第一方向相反的第二方向上相邻的两个有效区域的末端部分和设置在与第二方向相邻的两个有效区域的另一侧终端部分之间的第二延伸部分，第一和第二延伸部分 以循环配置连接两个活动区域。

公开(公告)号：US20080149913A1

公开(公告)日：2008-06-26

申请号：US11962862

申请日：2007-12-21

申请人： Hiroyasu TANAKA ,  Ryota Katsumata ,  Hideaki Aochi ,  Masaru Kito ,  Masaru Kidoh ,  Mitsuru Sato

发明人： Hiroyasu TANAKA ,  Ryota Katsumata ,  Hideaki Aochi ,  Masaru Kito ,  Masaru Kidoh ,  Mitsuru Sato

IPC分类号： H01L27/105 ,  H01L21/8239 ,  H01L45/00

CPC分类号： H01L27/2454 ,  G11C2213/71 ,  G11C2213/75 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/144 ,  H01L45/146

摘要： A semiconductor memory device is disclosed, which includes a first memory cell array formed on a semiconductor substrate and composed of a plurality of memory cells stacked in layers each having a characteristic change element and a vertical type memory cell transistor connected in parallel to each other, a plurality of second memory cell arrays formed on the semiconductor substrate and having the same structure as the first memory cell array, and arranged in an X direction with respect to the first memory cell array, and a plurality of third memory cell arrays formed on the semiconductor substrate and having the same structure as the first memory cell array, and arranged in a Y direction with respect to the first memory cell array, wherein a gate voltage is applied to gates of the vertical type memory cell transistors of the first to third memory cell arrays in a same layer.

摘要翻译： 公开了一种半导体存储器件，其包括形成在半导体衬底上的第一存储器单元阵列，并且由堆叠成各自具有彼此并联连接的特征变化元件和垂直型存储单元晶体管的多个存储单元组成， 多个第二存储单元阵列，形成在所述半导体衬底上并具有与所述第一存储单元阵列相同的结构，并且相对于所述第一存储单元阵列沿X方向布置;以及多个第三存储单元阵列， 半导体衬底并且具有与第一存储单元阵列相同的结构，并且相对于第一存储单元阵列在Y方向上布置，其中栅极电压被施加到第一至第三存储器的垂直型存储单元晶体管的栅极 单元阵列在同一层。

公开(公告)号：US20080118871A1

公开(公告)日：2008-05-22

申请号：US11795988

申请日：2006-01-27

申请人： Hideo Namatsu ,  Mitsuru Sato

发明人： Hideo Namatsu ,  Mitsuru Sato

IPC分类号： G03F7/26

CPC分类号： G03F7/40 ,  H01L21/0273

摘要： A fine and high-accuracy resist pattern, which is excellent in etching resistance, can be formed. Disclosed is a resist pattern forming method, which includes the steps of developing a resist composition having photosensitivity to a predetermined light source through a lithography technique to form a resist pattern 2 on a substrate 1, and bringing the resist pattern 2 into contact with a supercritical processing solution 5′ including a supercritical fluid 3′ which contains a crosslinking agent 4.

摘要翻译： 可以形成耐蚀刻性优异的精细且高精度的抗蚀剂图案。 公开了一种抗蚀剂图案形成方法，其包括通过光刻技术显影对预定光源具有光敏性的抗蚀剂组合物以在基板1上形成抗蚀剂图案2并使抗蚀剂图案2与超临界接触的步骤 处理溶液5'，其包含含有交联剂4的超临界流体3'。

公开(公告)号：US20070028203A1

公开(公告)日：2007-02-01

申请号：US11258176

申请日：2005-10-26

申请人： Mitsuru Sato ,  Hiroji Takeyama ,  Yuki Kumon ,  Tomoki Kanemochi

发明人： Mitsuru Sato ,  Hiroji Takeyama ,  Yuki Kumon ,  Tomoki Kanemochi

IPC分类号： G06F17/50

CPC分类号： G06F17/50

摘要： To create a function verification description, which is used for verifying a result of simulation performed on a finite state machine, irrespective of description languages of designing an FSM and creating the function verification description even by a person without knowledge of the language and the creation method of the function verification description, there is provided an apparatus including: an extracting section for extracting data concerning a performance that is a subject for the simulation from specification data of the FSM; a retaining section for retaining one or more description templates for function verification descriptions which are associated with one or more performances that are subjects for simulation; a selecting section for selecting a description template corresponding to the first performance; and a creating section for creating the function verifying description by substituting the data concerning the first performance into the particular description template selected.

摘要翻译： 为了创建功能验证描述，用于验证在有限状态机上执行的模拟结果，而不管设计FSM的描述语言以及甚至由没有语言知识的人创建功能验证描述和创建方法 提供了一种装置，包括：提取部分，用于从FSM的指定数据中提取与模拟对象的性能有关的数据; 一个保留部分，用于保存与作为模拟对象的一个​​或多个演奏相关联的功能验证描述的一个或多个描述模板; 选择部分，用于选择与第一演奏相对应的描述模板; 以及创建部分，用于通过将关于第一表演的数据替换到所选择的特定描述模板中来创建功能验证描述。

公开(公告)号：US07148148B2

公开(公告)日：2006-12-12

申请号：US10309198

申请日：2002-12-04

申请人： Yoshiaki Mori ,  Takuya Miyakawa ,  Mitsuru Sato ,  Shintaro Asuke ,  Kenichi Takagi

发明人： Yoshiaki Mori ,  Takuya Miyakawa ,  Mitsuru Sato ,  Shintaro Asuke ,  Kenichi Takagi

IPC分类号： H01L21/302

CPC分类号： H01L21/76838 ,  C25D5/022 ,  C25D7/12 ,  H01L21/0272 ,  H01L21/0274 ,  H01L21/288 ,  H01L21/31127 ,  H01L21/31133

摘要： A mask forming method that can reduce manufacturing cost is disclosed. The method forms a mask on the surface of a member to be processed in order to form a desired pattern using liquid material for patterning. The method also includes applying resist to the entire surface of the member to be processed, drying the applied resist, patterning by removing the resist in a pattern-formation area using photolithography, and heating the resist.

摘要翻译： 公开了一种降低制造成本的掩模形成方法。 该方法在待加工构件的表面上形成掩模，以便使用液体材料形成图案化所需的图案。 该方法还包括将抗蚀剂施加到待加工构件的整个表面，干燥所施加的抗蚀剂，通过使用光刻法去除图案形成区域中的抗蚀剂，并加热抗蚀剂来进行图案化。

公开(公告)号：US07098121B2

公开(公告)日：2006-08-29

申请号：US10367854

申请日：2003-02-19

申请人： Yoshiaki Mori ,  Takuya Miyakawa ,  Mitsuru Sato ,  Shintaro Asuke ,  Kenichi Takagi

发明人： Yoshiaki Mori ,  Takuya Miyakawa ,  Mitsuru Sato ,  Shintaro Asuke ,  Kenichi Takagi

IPC分类号： H01L21/22

CPC分类号： H01L21/3127 ,  H01L21/0212 ,  H01L21/02274 ,  H01L21/0272 ,  H01L21/0273 ,  H01L21/288 ,  H01L21/76838 ,  H01L27/1292

摘要： An object is to provide a mask formation method, which can curtail a manufacturing cost.A method of forming a film of predetermined pattern on the front surface of a member to-be-processed is so constructed as to carry out the step (S178) of improving the adherence of a pattern material solution to the member to-be-processed, the step (S180) of filling up a pattern forming recess provided in a mask on the surface of the member to-be-processed with a pattern material solution, the step (S186) of improving the film quality of the pattern film to-be-formed by processing the pattern material solution, the step (S188) of removing the pattern material solution having adhered on the mask, the step (S190) of drying the pattern material solution, and the step (S196) of subjecting the pattern film to annealing processing.

摘要翻译： 目的在于提供掩模形成方法，可以减少制造成本。 在待处理构件的正面上形成预定图案的膜的方法被构造成执行改善图案材料溶液与要被加工的构件的粘附的步骤（S 178） 在图案材料溶液的待处理部件的表面上填充设置在掩模中的图案形成用凹部的工序（S180），提高图案的膜质量的工序（S188） 通过处理图案材料溶液形成的薄膜，去除已经粘附在掩模上的图案材料溶液的步骤（S 188），干燥图案材料溶液的步骤（S190）和步骤（S1996） ）对图案膜进行退火处理。

公开(公告)号：US07091546B2

公开(公告)日：2006-08-15

申请号：US11038173

申请日：2005-01-21

申请人： Mitsuru Sato ,  Hirofumi Inoue ,  Masaru Kito

发明人： Mitsuru Sato ,  Hirofumi Inoue ,  Masaru Kito

IPC分类号： H01L29/772

CPC分类号： H01L27/10867

摘要： A semiconductor device includes semiconductor substrate, a trench capacitor formed in the semiconductor substrate, a cell transistor formed so as to the trench capacitor and having a gate electrode formed on the semiconductor substrate and a source/drain region formed in a surface of the semiconductor substrate, an impurity diffusion region formed in the semiconductor substrate so as to be electrically connected between the trench capacitor and the source/drain region, and a Ge inclusion region formed between the impurity diffusion region and the trench capacitor.

摘要翻译： 半导体器件包括半导体衬底，形成在半导体衬底中的沟槽电容器，形成为沟槽电容器的单元晶体管，并且具有形成在半导体衬底上的栅极电极和形成在半导体衬底的表面中的源极/漏极区域 形成在半导体衬底中以便电连接在沟槽电容器和源极/漏极区之间的杂质扩散区域和形成在杂质扩散区域和沟槽电容器之间的Ge包含区域。

公开(公告)号：US06907394B1

公开(公告)日：2005-06-14

申请号：US09570389

申请日：2000-05-12

申请人： Mitsuru Sato

发明人： Mitsuru Sato

IPC分类号： G01R31/28 ,  G06F9/45 ,  G06F17/50 ,  G06G7/62 ,  H01L21/82

CPC分类号： G06F17/5022 ,  G06F17/5036

摘要： A device for simulating circuits is provided with an identifying system and a verifying system. The identifying system identifies a pair of wires in which two signals operate simultaneously within an appointed period and a pair of wires in which two signals do not operate almost simultaneously within the appointed period. The verifying system verifies actions of a circuit to be analyzed, under an assumption that the coupling capacitor between the pair of wires in which it is judged by the identifying system that two signals do not simultaneously operate within the appointed period is a ground capacitor.

摘要翻译： 用于模拟电路的装置设置有识别系统和验证系统。 识别系统识别一条电线，其中两个信号在指定时间段内同时操作，并且一对电线，其中两个信号在指定时段内几乎不同时操作。 验证系统验证要分析的电路的动作，假设由识别系统判断两条信号在指定时段内不同时工作的一对导线之间的耦合电容器是接地电容器。

公开(公告)号：US20050095801A1

公开(公告)日：2005-05-05

申请号：US10947388

申请日：2004-09-23

申请人： Mitsuru Sato ,  Hirofumi Inoue

发明人： Mitsuru Sato ,  Hirofumi Inoue

IPC分类号： H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94 ,  H01L21/20 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L27/1087 ,  H01L27/10829 ,  H01L27/10867 ,  H01L29/66181 ,  H01L29/945

摘要： A trench capacitor comprises a semiconductor substrate, a trench provided in the semiconductor substrate, a first doped polysilicon filled in the trench at a lower end of the trench via a first dielectric film, and a second doped polysilicon filled in the trench at an upper end of the trench via a second dielectric film, the second doped polysilicon being contiguously disposed to the first doped polycrystal silicon, wherein the second dielectric film consists of an oxide film using radicals.

摘要翻译： 沟槽电容器包括半导体衬底，设置在半导体衬底中的沟槽，经由第一电介质膜填充在沟槽的下端处的沟槽中的第一掺杂多晶硅，以及在上端填充在沟槽中的第二掺杂多晶硅 的第二电介质膜，所述第二掺杂多晶硅连续地设置在所述第一掺杂多晶硅上，其中所述第二电介质膜由使用自由基的氧化膜组成。

公开(公告)号：US06657877B2

公开(公告)日：2003-12-02

申请号：US09966769

申请日：2001-09-28

申请人： Masato Kashima ,  Mitsuru Sato ,  Eiji Kuroda ,  Hironobu Shiroyama

发明人： Masato Kashima ,  Mitsuru Sato ,  Eiji Kuroda ,  Hironobu Shiroyama

IPC分类号： H02M7217

CPC分类号： H02M7/217 ,  H02M3/156

摘要： A power supply circuit improves the power factor when the load is light, and incorporates a starting circuit for reacting quickly to the changes in the output from the power supply circuit and a short-circuit detecting means for detecting the short-circuit of the feedback signal. The apparatus includes: an error amplifier; a comparator that monitors the output from the error amplifier and generates an offset regulating current ISO; a multiplier; a sensing current comparator that compares the output signal from the multiplier and the AC line current and generates a reset signal; a timer that directly monitors the inputted zero-cross signal; and a comparator for short-circuit detection, that facilitates reducing the exterior parts and components.