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179 条记录 (耗时 0.055 秒)

    Substrate and method for producing a substrate
    21.
    发明申请
    Substrate and method for producing a substrate 有权
    基板及其制造方法

    公开(公告)号：US20050110088A1

    公开(公告)日：2005-05-26

    申请号：US10968846

    申请日：2004-10-18

    申请人： Franz Hofmann ,  Richard Luyken ,  Wolfgang Roesner ,  Michael Specht ,  Martin Stadele

    发明人： Franz Hofmann ,  Richard Luyken ,  Wolfgang Roesner ,  Michael Specht ,  Martin Stadele

    IPC分类号： H01L21/20 ,  H01L21/762 ,  H01L27/01

    CPC分类号： H01L21/76254

    摘要： Substrate having a first partial substrate with a carrier layer and a second partial substrate, which is bonded to the first partial substrate. The second partial substrate has an insulator layer, which is applied on the carrier layer and has at least two regions each having a different thickness, thereby forming a stepped surface of the insulator layer, and a semiconductor layer, which is applied to the stepped surface of the insulator layer and is formed at least partially epitaxially, wherein the semiconductor layer has a planar surface which is opposite to the stepped surface of the insulator layer. Transistors are formed on the semiconductor layer.

    摘要翻译： 衬底，具有第一部分衬底和载体层，第二部分衬底与第一部分衬底结合。 第二部分基板具有绝缘体层，其被施加在载体层上并且具有至少两个各自具有不同厚度的区域，从而形成绝缘体层的台阶表面，以及施加到台阶表面的半导体层 并且至少部分地外延形成，其中半导体层具有与绝缘体层的台阶表面相对的平面。 在半导体层上形成晶体管。

    Production method for a FinFET transistor arrangement, and corresponding FinFET transistor arrangement
    22.
    发明授权
    Production method for a FinFET transistor arrangement, and corresponding FinFET transistor arrangement 有权
    FinFET晶体管布置的制造方法和相应的FinFET晶体管布置

    公开(公告)号：US07692246B2

    公开(公告)日：2010-04-06

    申请号：US11649470

    申请日：2007-01-04

    申请人： Lars Dreeskornfeld ,  Franz Hofmann ,  Johannes Richard Luyken ,  Michael Specht

    发明人： Lars Dreeskornfeld ,  Franz Hofmann ,  Johannes Richard Luyken ,  Michael Specht

    IPC分类号： H01L27/01

    CPC分类号： H01L21/823412 ,  H01L21/823437 ,  H01L29/66818 ,  H01L29/7851

    摘要： The present invention provides a FinFET transistor arrangement produced using a method with the steps: providing a substrate (106, 108); forming an active region (1) on the substrate a fin-like channel region (113b′; 113b″). Formation of the fin-like channel region (113b′; 113b″) has the following steps: forming a hard mask (S1-S4) on the active region (1); anisotropic etching of the active region (1) using the hard mask (S1-S4) forming STI trenches (G1-G5) having an STI oxide filling (9); polishing-back of the STI oxide filling (9); etching-back of the polished-back STI oxide filling (9); selective removal of components of the hard mask forming a modified hard mask (S1′-S4′); anisotropic etching of the active region (1) using the modified hard mask (S1′-S4′) forming widened STI trenches (G1′-G5′), the fin-like channel regions (113b′; 113b″) of the active region (1) remaining for each individual FinFET transistor.

    摘要翻译： 本发明提供一种使用以下步骤制造的FinFET晶体管布置：步骤：提供衬底（106,108）; 在所述衬底上形成鳍状沟道区（113b'; 113b“）上的有源区（1）。 翅片状通道区域（113b'; 113b“）的形成步骤如下：在有源区域（1）上形成硬掩模（S1-S4）; 使用形成具有STI氧化物填充物（9）的STI沟槽（G1-G5）的硬掩模（S1-S4）对有源区域（1）进行各向异性蚀刻。 STI氧化物填充物（9）的抛光; 抛光后的STI氧化物填充物（9）的回蚀; 选择性地去除形成修改的硬掩模（S1'-S4'）的硬掩模的部件; 使用形成加宽的STI沟槽（G1'-G5'）的修改的硬掩模（S1'-S4'）对有源区（1）进行各向异性蚀刻，有源区的鳍状沟道区（113b'; 113b“） （1）保留每个单独的FinFET晶体管。

    Semiconductor memory component
    23.
    发明申请
    Semiconductor memory component 失效
    半导体存储器组件

    公开(公告)号：US20060267082A1

    公开(公告)日：2006-11-30

    申请号：US11438883

    申请日：2006-05-23

    申请人： Franz Hofmann ,  Richard Luyken ,  Wolfgang Roesner ,  Michael Specht ,  Martin Staedele

    发明人： Franz Hofmann ,  Richard Luyken ,  Wolfgang Roesner ,  Michael Specht ,  Martin Staedele

    IPC分类号： H01L29/76

    CPC分类号： H01L27/108 ,  H01L27/10802 ,  H01L27/1203

    摘要： A semiconductor memory component comprises at least one memory cell. The memory cell comprises a semiconductor body comprised of a body region, a drain region and a source region, a gate dielectric, and a gate electrode. The body region comprises a first conductivity type and a depression between the source and drain regions, and the source and drain regions comprise a second conductivity type. The gate electrode is arranged at least partly in the depression and is insulated from the body, source, and drain regions by the gate dielectric. The body region further comprises a first continuous region with a first dopant concentration and a second continuous region with a second dopant concentration greater than the first dopant concentration. The first continuous region adjoins the drain region, the depression and the source region, and the second region is arranged below the first region and adjoins the first region.

    摘要翻译： 半导体存储器组件包括至少一个存储单元。 存储单元包括由体区，漏区和源区组成的半导体本体，栅电介质和栅电极。 主体区域包括第一导电类型和源极和漏极区域之间的凹陷，并且源极和漏极区域包括第二导电类型。 栅电极至少部分地布置在凹陷中，并且通过栅极电介质与主体，源极和漏极区绝缘。 体区还包括具有第一掺杂剂浓度的第一连续区域和具有大于第一掺杂剂浓度的第二掺杂剂浓度的第二连续区域。 第一连续区域邻接漏极区域，凹陷部分和源极区域，并且第二区域布置在第一区域下方并与第一区域相邻。

    Method for the production of a memory cell, memory cell and memory cell arrangement
    25.
    发明申请
    Method for the production of a memory cell, memory cell and memory cell arrangement 有权
    用于生产存储器单元，存储单元和存储单元布置的方法

    公开(公告)号：US20050157583A1

    公开(公告)日：2005-07-21

    申请号：US10999810

    申请日：2004-11-29

    申请人： Franz Hofmann ,  Richard Luyken ,  Michael Specht

    发明人： Franz Hofmann ,  Richard Luyken ,  Michael Specht

    IPC分类号： G11C16/04 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L21/84 ,  H01L27/115 ,  H01L27/12 ,  H01L29/788 ,  G11C8/02

    CPC分类号： H01L21/28273 ,  G11C16/0416 ,  G11C16/0483 ,  H01L21/28282 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/1203 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7883

    摘要： Memory cell having an auxiliary substrate, on which a first gate insulating layer is formed, a floating gate formed on the first gate insulating layer, an electrically insulating layer formed on the floating gate, a memory gate electrode formed on the electrically insulating layer, a substrate fixed to the memory gate electrode, a second gate insulating layer formed on a part of a surface of the auxiliary substrate, which surface is uncovered by partially removing the auxiliary substrate, a read gate electrode formed on the second gate insulating layer, and two source/drain regions located between a channel region essentially in and/or on a surface region of the remaining material of the auxiliary substrate that is free of the second gate insulating layer and the read gate electrode, the channel region being arranged in each case at least partly laterally overlapping the floating gate and the read gate electrode.

    摘要翻译： 具有辅助基板的存储单元，其上形成有第一栅极绝缘层，形成在第一栅极绝缘层上的浮动栅极，形成在浮动栅极上的电绝缘层，形成在电绝缘层上的存储栅电极， 基板固定到存储栅电极，第二栅极绝缘层，形成在辅助基板的表面的一部分上，该表面通过部分去除辅助基板而被覆盖，形成在第二栅极绝缘层上的读取栅电极和两个 源极/漏极区域位于基本上在辅助衬底的剩余材料的表面区域和/或栅极绝缘层之间的沟道区域之间，沟道区域分别布置在 至少部分地侧向地重叠浮置栅极和读取栅电极。