公开(公告)号：US20060043454A1

公开(公告)日：2006-03-02

申请号：US10711144

申请日：2004-08-27

申请人： Douglas Coolbaugh ,  Douglas Hershberger ,  Robert Rassel

发明人： Douglas Coolbaugh ,  Douglas Hershberger ,  Robert Rassel

IPC分类号： H01L29/94 ,  H01L21/20

CPC分类号： H01L29/93 ,  H01L29/94

摘要： The present invention provides a varactor that has increased tunability and a high quality factor Q as well as a method of fabricating the varactor. The method of the present invention can be integrated into a conventional CMOS processing scheme or into a conventional BiCMOS processing scheme. The method includes providing a structure that includes a semiconductor substrate of a first conductivity type and optionally a subcollector or isolation well (i.e., doped region) of a second conductivity type located below an upper region of the substrate, the first conductivity type is different from said second conductivity type. Next, a plurality of isolation regions are formed in the upper region of the substrate and then a well region is formed in the upper region of the substrate. In some cases, the doped region is formed at this point of the inventive process. The well region includes outer well regions of the second conductivity type and an inner well region of the first conductivity type. Each well of said well region is separated at an upper surface by an isolation region. A field effect transistor having at least a gate conductor of the first conductivity type is then formed above the inner well region.

摘要翻译： 本发明提供一种具有增加的可调性和高品质因数Q的变容二极管以及制造变容二极管的方法。 本发明的方法可以集成到常规的CMOS处理方案中，或者被整合到常规的BiCMOS处理方案中。 该方法包括提供包括第一导电类型的半导体衬底和位于衬底的上部区域下方的第二导电类型的子集电极或隔离阱（即，掺杂区）的结构，第一导电类型不同于 所述第二导电类型。 接下来，在基板的上部区域形成多个隔离区域，然后在基板的上部区域形成阱区域。 在一些情况下，在本发明方法的这一点形成掺杂区域。 阱区包括第二导电类型的外阱区和第一导电类型的内阱区。 所述阱区的每个阱在上表面被隔离区分开。 然后形成至少具有第一导电类型的栅极导体的场效应晶体管，并在内部阱区域的上方形成。

公开(公告)号：US20050161770A1

公开(公告)日：2005-07-28

申请号：US11004877

申请日：2004-12-07

申请人： Douglas Coolbaugh ,  Stephen Furkay ,  Jeffrey Johnson ,  Robert Rassel ,  David Sheridan

发明人： Douglas Coolbaugh ,  Stephen Furkay ,  Jeffrey Johnson ,  Robert Rassel ,  David Sheridan

IPC分类号： H01L29/93 ,  H01L29/94 ,  H01L27/108

CPC分类号： H01L29/93 ,  H01L29/94

摘要： A method and device providing a HA junction varactor which may be fabricated with a reduced variation in C-V tuning curve from one varactor to the next. The process produces a varactor with an active region formed substantially by doping an Si substrate with various dopants at various energy levels. Accordingly, unit-to-unit device variation is reduced because etching, growing, and deposition processes to make the active portion of the varactor are reduced or eliminated. The resulting HA junction has a more uniform thickness, and a more uniform doping profile.

摘要翻译： 提供HA结变容二极管的方法和装置，其可以以从一个变容二极管到下一个变容二极管的C-V调谐曲线的变化减小来制造。 该方法产生可变电抗器，其中有源区基本上通过以各种能级掺杂各种掺杂剂的Si衬底而形成。 因此，由于蚀刻，生长和沉积工艺以使变容二极管的活性部分减少或消除，因此减小了单元到单元的装置变化。 所得到的HA结具有更均匀的厚度和更均匀的掺杂分布。

公开(公告)号：US20050161769A1

公开(公告)日：2005-07-28

申请号：US10707905

申请日：2004-01-23

申请人： Douglas Coolbaugh ,  Stephen Furkay ,  Jeffrey Johnson ,  Robert Rassel ,  David Sheridan

发明人： Douglas Coolbaugh ,  Stephen Furkay ,  Jeffrey Johnson ,  Robert Rassel ,  David Sheridan

IPC分类号： H01L29/93 ,  H01L29/94

CPC分类号： H01L29/93 ,  H01L29/94

摘要： A method and device providing a HA junction varactor which may be fabricated with a reduced variation in C-V tuning curve from one varactor to the next. The process produces a varactor with an active region formed substantially by doping an Si substrate with various dopants at various energy levels. Accordingly, unit-to-unit device variation is reduced because etching, growing, and deposition processes to make the active portion of the varactor are reduced or eliminated. The resulting HA junction has a more uniform thickness, and a more uniform doping profile.

摘要翻译： 提供HA结变容二极管的方法和装置，其可以以从一个变容二极管到下一个变容二极管的C-V调谐曲线的变化减小来制造。 该方法产生可变电抗器，其中有源区基本上通过以各种能级掺杂各种掺杂剂的Si衬底而形成。 因此，由于蚀刻，生长和沉积工艺以使变容二极管的活性部分减少或消除，因此减小了单元到单元的装置变化。 所得到的HA结具有更均匀的厚度和更均匀的掺杂分布。

公开(公告)号：US20050070102A1

公开(公告)日：2005-03-31

申请号：US10605439

申请日：2003-09-30

申请人： Douglas Coolbaugh ,  Heidi Greer ,  Robert Rassel

发明人： Douglas Coolbaugh ,  Heidi Greer ,  Robert Rassel

IPC分类号： H01L20060101 ,  H01L21/02 ,  H01L21/302 ,  H01L21/461 ,  H01L27/08

CPC分类号： H01L27/0738 ,  H01L27/0802 ,  H01L28/20

摘要： A process is disclosed for fabricating precision polysilicon resistors which more precisely control the tolerance of the sheet resistivity of the produced polysilicon resistors. The process generally includes performing an emitter/FET activation rapid thermal anneal (RTA) on a wafer having partially formed polysilicon resistors, followed by steps of depositing a protective dielectric layer on the polysilicon, implanting a dopant through the protective dielectric layer into the polysilicon to define the resistance of the polysilicon resistors, and forming a silicide.

摘要翻译： 公开了一种制造精密多晶硅电阻器的方法，其更精确地控制所产生的多晶硅电阻器的薄层电阻率的公差。 该方法通常包括在具有部分形成的多晶硅电阻器的晶片上执行发射极/ FET激活快速热退火（RTA），随后是在多晶硅上沉积保护性介电层的步骤，将掺杂剂通过保护电介质层注入到多晶硅中 限定多晶硅电阻器的电阻，并形成硅化物。

公开(公告)号：US20080099787A1

公开(公告)日：2008-05-01

申请号：US11873696

申请日：2007-10-17

申请人： Douglas Coolbaugh ,  Alvin Joseph ,  Seong-dong Kim ,  Louis Lanzerotti ,  Xuefeng Liu ,  Robert Rassel

发明人： Douglas Coolbaugh ,  Alvin Joseph ,  Seong-dong Kim ,  Louis Lanzerotti ,  Xuefeng Liu ,  Robert Rassel

IPC分类号： H01L27/06

CPC分类号： H01L27/0814 ,  H01L27/0664 ,  H01L27/0823 ,  H01L29/0821 ,  H01L29/7371 ,  H01L29/868

摘要： A structure comprises a single wafer with a first subcollector formed in a first region having a first thickness and a second subcollector formed in a second region having a second thickness, different from the first thickness. A method is also contemplated which includes providing a substrate including a first layer and forming a first doped region in the first layer. The method further includes forming a second layer on the first layer and forming a second doped region in the second layer. The second doped region is formed at a different depth than the first doped region. The method also includes forming a first reachthrough in the first layer and forming a second reachthrough in second layer to link the first reachthrough to the surface.

摘要翻译： 一种结构包括具有形成在具有第一厚度的第一区域中的第一子集电极的单晶片和形成在具有不同于第一厚度的第二厚度的第二区域中的第二子集电极。 还可以设想一种方法，其包括提供包括第一层并在第一层中形成第一掺杂区的衬底。 该方法还包括在第一层上形成第二层并在第二层中形成第二掺杂区域。 第二掺杂区形成在与第一掺杂区不同的深度。 该方法还包括在第一层中形成第一通道并在第二层中形成第二通道以将第一通道连接到表面。

公开(公告)号：US20080067623A1

公开(公告)日：2008-03-20

申请号：US11944839

申请日：2007-11-26

申请人： Douglas Coolbaugh ,  Jeffrey Johnson ,  Xuefeng Liu ,  Bradley Orner ,  Robert Rassel ,  David Sheridan

发明人： Douglas Coolbaugh ,  Jeffrey Johnson ,  Xuefeng Liu ,  Bradley Orner ,  Robert Rassel ,  David Sheridan

IPC分类号： H01L29/872

CPC分类号： H01L29/872 ,  H01L29/0657 ,  H01L29/417 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/861 ,  H01L29/868

摘要： A structure and method of fabricating lateral diodes. The diodes include Schottky diodes and PIN diodes. The method of fabrication includes forming one or more doped regions and more trenches in a silicon substrate and forming metal silicides on the sidewalls of the trenches. The fabrication of lateral diodes may be integrated with the fabrication of field effect, bipolar and SiGe bipolar transistors.

摘要翻译： 制造横向二极管的结构和方法。 二极管包括肖特基二极管和PIN二极管。 制造方法包括在硅衬底中形成一个或多个掺杂区域和更多沟槽，并在沟槽的侧壁上形成金属硅化物。 横向二极管的制造可以与场效应，双极和SiGe双极晶体管的制造集成。

公开(公告)号：US20060166454A1

公开(公告)日：2006-07-27

申请号：US10905940

申请日：2005-01-27

申请人： Douglas Coolbaugh ,  John Florkey ,  Robert Rassel

发明人： Douglas Coolbaugh ,  John Florkey ,  Robert Rassel

IPC分类号： H01L21/20

CPC分类号： H01L21/26513 ,  H01L27/0802 ,  H01L28/20

摘要： Various methods of fabricating a high precision, silicon-containing resistor in which the resistor is formed as a discrete device integrated in complementary metal oxide semiconductor (CMOS) processing utilizing low temperature silicidation are provided. In some embodiments, the Si-containing layer is implanted with a high dose of ions prior to activation. The activation can be performed by the deposition of a protective dielectric layer, or a separate activation anneal. In another embodiment, a highly doped in-situ Si-containing layer is used thus eliminating the need for implanting into the Si-containing layer.

摘要翻译： 提供制造高精度含硅电阻器的各种方法，其中电阻器形成为集成在利用低温硅化物的互补金属氧化物半导体（CMOS）处理中的分立器件）。 在一些实施方案中，在活化之前，用高剂量的离子注入含Si层。 激活可以通过沉积保护性介电层或单独的激活退火来进行。 在另一个实施方案中，使用高掺杂的原位含Si层，因此不需要植入含Si层。

公开(公告)号：US20060046418A1

公开(公告)日：2006-03-02

申请号：US10711130

申请日：2004-08-26

申请人： Douglas Coolbaugh ,  Heidi Greer ,  Robert Rassel

发明人： Douglas Coolbaugh ,  Heidi Greer ,  Robert Rassel

IPC分类号： H01L21/20

CPC分类号： H01L21/2652 ,  H01C17/26 ,  H01C17/265 ,  H01L28/20

摘要： A method of fabricating a resistor in which the resistance value of the resistor is measured and adjusted after silicidation is provided. The method of the present invention begins with first providing at least one resistor, e.g., polysilicon, having a resistance value on a surface of a semiconductor substrate. The at least one resistor has been subjected to a silicidation process. Next, the resistance value of the at least one resistor is measured to determine the actual resistance of the resistor after silicidation. After the measuring step, the resistance of the resistor is adjusted to achieve a desired resistance value. The adjusting may include a post silicidation rapid thermal anneal and/or a post silicidation ion implantation and a low temperature rapid thermal anneal step.

摘要翻译： 提供了在硅化后测量和调整电阻器的电阻值的电阻器的制造方法。 本发明的方法首先开始在半导体衬底的表面上提供具有电阻值的至少一个电阻器，例如多晶硅。 至少一个电阻器已进行硅化处理。 接下来，测量至少一个电阻器的电阻值，以确定硅化后电阻器的实际电阻。 在测量步骤之后，调整电阻器的电阻以获得所需的电阻值。 调整可以包括后硅化快速热退火和/或后硅化离子注入和低温快速热退火步骤。

公开(公告)号：US20070241421A1

公开(公告)日：2007-10-18

申请号：US11279934

申请日：2006-04-17

申请人： Xuefeng Liu ,  Robert Rassel ,  Steven Voldman

发明人： Xuefeng Liu ,  Robert Rassel ,  Steven Voldman

IPC分类号： H01L21/331 ,  H01L29/00

CPC分类号： H01L29/7322 ,  H01L27/0921 ,  H01L29/0821 ,  H01L29/66272

摘要： A structure comprises a deep subcollector buried in a first region of a dual epitaxial layer and a reachthrough structure in contact with the deep subcollector to provide a low-resistive shunt which prevents CMOS latch-up for a first device. The structure may additionally include a near subcollector formed in a higher region than the deep subcollector and under another device. At least one reachthrough electrically connects the deep subcollector and the near subcollector. The method includes forming a merged triple well double epitaxy/double subcollector.

摘要翻译： 一种结构包括埋藏在双外延层的第一区域中的深子集电极和与深子集电极接触的到达结构，以提供阻止第一器件的CMOS闩锁的低电阻分流。 该结构可以另外包括形成在比深层子集电极更高的区域内并且在另一器件下形成的近子集电极。 至少一个通孔电连接深子集电极和近子集电极。 该方法包括形成合并三阱双外延/双子集电极。