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    SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE
    1.
    发明申请
    SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE 失效
    半导体结构及其制造方法

    公开(公告)号：US20070241421A1

    公开(公告)日：2007-10-18

    申请号：US11279934

    申请日：2006-04-17

    申请人： Xuefeng Liu ,  Robert Rassel ,  Steven Voldman

    发明人： Xuefeng Liu ,  Robert Rassel ,  Steven Voldman

    IPC分类号： H01L21/331 ,  H01L29/00

    CPC分类号： H01L29/7322 ,  H01L27/0921 ,  H01L29/0821 ,  H01L29/66272

    摘要： A structure comprises a deep subcollector buried in a first region of a dual epitaxial layer and a reachthrough structure in contact with the deep subcollector to provide a low-resistive shunt which prevents CMOS latch-up for a first device. The structure may additionally include a near subcollector formed in a higher region than the deep subcollector and under another device. At least one reachthrough electrically connects the deep subcollector and the near subcollector. The method includes forming a merged triple well double epitaxy/double subcollector.

    摘要翻译： 一种结构包括埋藏在双外延层的第一区域中的深子集电极和与深子集电极接触的到达结构，以提供阻止第一器件的CMOS闩锁的低电阻分流。 该结构可以另外包括形成在比深层子集电极更高的区域内并且在另一器件下形成的近子集电极。 至少一个通孔电连接深子集电极和近子集电极。 该方法包括形成合并三阱双外延/双子集电极。

    SEMICONDUCTOR DEVICES
    2.
    发明申请
    SEMICONDUCTOR DEVICES 有权
    半导体器件

    公开(公告)号：US20080036029A1

    公开(公告)日：2008-02-14

    申请号：US11870567

    申请日：2007-10-11

    申请人： Xuefeng LIU ,  Rober Rassel ,  Steven Voldman

    发明人： Xuefeng LIU ,  Rober Rassel ,  Steven Voldman

    IPC分类号： H01L29/00

    CPC分类号： H01L29/7436 ,  H01L27/0262 ,  H01L29/7378

    摘要： A design structure embodied in a machine readable medium used in a design process. The design structure includes a first sub-collector formed in an upper portion of a substrate and a lower portion of a first epitaxial layer, and a second sub-collector formed in an upper portion of the first epitaxial layer and a lower portion of a second epitaxial layer. The design structure additionally includes a reach-through structure connecting the first and second sub-collectors, and an N-well formed in a portion of the second epitaxial layer and in contact with the second sub-collector and the reach-through structure. Also, the design structure includes N+ diffusion regions in contact with the N-well, a P+ diffusion region within the N-well, and shallow trench isolation structures between the N+ and P+ diffusion regions.

    摘要翻译： 在设计过程中使用的机器可读介质中体现的设计结构。 该设计结构包括形成在衬底的上部和第一外延层的下部的第一子集电极和形成在第一外延层的上部中的第二子集电极， 外延层。 该设计结构还包括连接第一和第二子集电器的通孔结构以及形成在第二外延层的一部分中并与第二子集电极和达到通孔结构接触的N阱。 此外，设计结构包括与N阱接触的N +扩散区域，N阱内的P +扩散区域和N +和P +扩散区域之间的浅沟槽隔离结构。

    LATERAL LUBISTOR STRUCTURE AND METHOD
    4.
    发明申请
    LATERAL LUBISTOR STRUCTURE AND METHOD 有权
    侧向劳工组织结构与方法

    公开(公告)号：US20060273372A1

    公开(公告)日：2006-12-07

    申请号：US10908961

    申请日：2005-06-02

    申请人： Steven Voldman ,  Jack Mandelman

    发明人： Steven Voldman ,  Jack Mandelman

    IPC分类号： H01L27/108

    CPC分类号： H01L29/7391 ,  H01L27/0248 ,  H01L27/1203 ,  H01L29/785 ,  H01L2029/7857

    摘要： An ESD LUBISTOR structure based on FINFET technology employs a vertical fin (a thin vertical member containing the source, drain and body of the device) in alternatives with and without a gate. The gate may be connected to the external electrode being protected to make a self-activating device or may be connected to a reference voltage. The device may be used in digital or analog circuits.

    摘要翻译： 基于FINFET技术的ESD LUBISTOR结构在具有和不具有栅极的情况下采用垂直翅片（包含装置的源极，漏极和主体的薄垂直构件）。 栅极可以连接到受保护的外部电极以形成自激活装置或者可以连接到参考电压。 该器件可用于数字或模拟电路。

    DENDRITE GROWTH CONTROL CIRCUIT
    6.
    发明申请
    DENDRITE GROWTH CONTROL CIRCUIT 有权

    公开(公告)号：US20060110909A1

    公开(公告)日：2006-05-25

    申请号：US10904680

    申请日：2004-11-23

    申请人： Douglas Hershberger ,  Steven Voldman ,  Michael Zierak

    发明人： Douglas Hershberger ,  Steven Voldman ,  Michael Zierak

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76838

    摘要： A circuit is provided which prevents dendrite formation on interconnects during semiconductor device processing due to a dendrite-forming current. The circuit includes a switch located in at least one of the dendrite-forming current paths. The switch is configured to be open or in the “off” state during processing, and is configured to be closed or in the “on” state after processing to allow proper functioning of the semiconductor device. The switch may include an nFET or pFET, depending on the environment in which it is used to control or prevent dendrite formation. The switch may be configured to change to the “closed” state when an input signal is provided during operation of the fabricated semiconductor device.

    OPTIMIZED SCHEDULING BASED ON SENSITIVITY DATA
    7.
    发明申请
    OPTIMIZED SCHEDULING BASED ON SENSITIVITY DATA 有权
    基于敏感性数据的优化调度

    公开(公告)号：US20050283265A1

    公开(公告)日：2005-12-22

    申请号：US10710065

    申请日：2004-06-16

    申请人： Brian Denton ,  Cuc Huynh ,  Shreesh Tandel ,  Steven Voldman

    发明人： Brian Denton ,  Cuc Huynh ,  Shreesh Tandel ,  Steven Voldman

    IPC分类号： G06F19/00

    CPC分类号： G06Q10/06

    摘要： A scheduling optimizer system, method and program product that analyzes a device for sensitivities, such as ESD sensitivities, and allows for modification of a floor schedule of the assembly unit of the device based on the sensitivity of the device while improving the overall performance of the assembly unit are disclosed. The scheduling optimizer analyzes sensitivity data for a device during operation of the assembly unit on the floor schedule. The floor schedule is then optimized based on the analyzed sensitivity data.

    摘要翻译： 调度优化器系统，方法和程序产品，用于分析设备的灵敏度，如ESD灵敏度，并允许基于设备的灵敏度修改设备的组装单元的楼层调度，同时提高整体性能 公开了组装单元。 调度优化器根据楼层进度分析装配单元运行期间设备的灵敏度数据。 然后根据分析的灵敏度数据优化楼层进度。

    HIGH TOLERANCE TCR BALANCED HIGH CURRENT RESISTOR FOR RF CMOS AND RF SiGe BiCMOS APPLICATIONS AND CADENCED BASED HIERARCHICAL PARAMETERIZED CELL DESIGN KIT WITH TUNABLE TCR AND ESD RESISTOR BALLASTING FEATURE
    8.
    发明申请
    HIGH TOLERANCE TCR BALANCED HIGH CURRENT RESISTOR FOR RF CMOS AND RF SiGe BiCMOS APPLICATIONS AND CADENCED BASED HIERARCHICAL PARAMETERIZED CELL DESIGN KIT WITH TUNABLE TCR AND ESD RESISTOR BALLASTING FEATURE 失效
    用于RF CMOS和RF SiGe BiCMOS应用的高耐压TCR平衡型高电流电阻器和基于CAD的分层式参数化电池设计套件，具有TUNABLE TCR和ESD电阻贴片特性

    公开(公告)号：US20050156281A1

    公开(公告)日：2005-07-21

    申请号：US10707863

    申请日：2004-01-19

    申请人： Ebenezer Eshun ,  Steven Voldman

    发明人： Ebenezer Eshun ,  Steven Voldman

    IPC分类号： H01C7/06 ,  H01L21/02 ,  H01L21/20 ,  H01L23/62 ,  H01L27/02 ,  H01L27/08 ,  H01L29/00

    CPC分类号： H01C7/06 ,  H01L27/0288 ,  H01L27/0802 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A resistor device structure and method of manufacture therefore, wherein the resistor device structure invention includes a plurality of alternating conductive film and insulative film layers, at least two of the conductive film layers being electrically connected in parallel to provide for high current flow through the resistor device at high frequencies with increased temperature and mechanical stability. The alternating conductive film and insulative film layers may be of a planar or non-planar geometric spatial orientation. The alternating conductive film and insulative film layers may include lateral and vertical portions designed to enable a uniform current density flow within the structure itself through a self-ballasting effect within the physical resistor. A computer aided design tool with graphical and schematic features is provided to enable generation of hierarchical parameterized cells for a resistor element with the ability to provide customization, personalization and tunability of TCR, TCR matching, and high current and ESD robustness.

    摘要翻译： 因此，电阻器件结构及其制造方法，其中电阻器件结构发明包括多个交替导电膜和绝缘膜层，至少两个导电膜层并联电连接以提供通过电阻器的高电流 器件在高频下具有升高的温度和机械稳定性。 交替导电膜和绝缘膜层可以是平面或非平面的几何空间取向。 交替导电膜和绝缘膜层可以包括横向和垂直部分，其被设计成能够通过物理电阻器内的自镇流效应在结构本身内实现均匀的电流密度流动。 提供了具有图形和原理图功能的计算机辅助设计工具，以便能够为电阻元件生成分层参数化单元，具有提供TCR，TCR匹配以及高电流和ESD鲁棒性的定制，个性化和可调性的能力。

    INTER-CHIP ESD PROTECTION STRUCTURE FOR HIGH SPEED AND HIGH FREQUENCY DEVICES
    10.
    发明申请
    INTER-CHIP ESD PROTECTION STRUCTURE FOR HIGH SPEED AND HIGH FREQUENCY DEVICES 有权
    用于高速和高频器件的片间ESD保护结构

    公开(公告)号：US20070029646A1

    公开(公告)日：2007-02-08

    申请号：US11161414

    申请日：2005-08-02

    申请人： Steven Voldman

    发明人： Steven Voldman

    IPC分类号： H01L39/00

    CPC分类号： H01L23/60 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/0508 ,  H01L2224/051 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/056 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06531 ,  H01L2924/12044 ,  H01L2924/3011 ,  H01L2924/00014

    摘要： The present invention relates to inter-chip electrostatic discharge (ESD) protection structures for high speed, and high frequency devices that contain one or more direct, inter-chip signal transmission paths. Specifically, the present invention relates to a structure that contains: (1) a first chip including a first circuit, (2) a second chip including a second circuit, (3) an intermediate insulator layer located between the first and second chips, wherein the first and second circuits form a signal transmission path for transmitting signals through the intermediate insulator layer. An electrostatic discharge (ESD) protection path is provided in the structure between the first and the second chip through the intermediate insulator layer, to protect the signal transmission path from ESD damages.

    摘要翻译： 本发明涉及用于高速的片上静电放电（ESD）保护结构以及包含一个或多个直接的芯片间信号传输路径的高频器件。 具体而言，本发明涉及一种结构，其包括：（1）包括第一电路的第一芯片，（2）包括第二电路的第二芯片，（3）位于第一和第二芯片之间的中间绝缘体层，其中 第一和第二电路形成用于通过中间绝缘体层传输信号的信号传输路径。 通过中间绝缘层在第一和第二芯片之间的结构中提供静电放电（ESD）保护路径，以保护信号传输路径免受ESD损害。