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34 条记录 (耗时 0.024 秒)

    METHOD AND APPARATUS FOR DYNAMIC CHARACTERIZATION OF RELIABILITY WEAROUT MECHANISMS
    21.
    发明申请
    METHOD AND APPARATUS FOR DYNAMIC CHARACTERIZATION OF RELIABILITY WEAROUT MECHANISMS 失效
    用于动态表征可靠性磨损机制的方法和装置

    公开(公告)号：US20090167336A1

    公开(公告)日：2009-07-02

    申请号：US11968444

    申请日：2008-01-02

    申请人： Giuseppe La Rosa ,  Kevin Kolvenbach ,  Ping-Chuan Wang ,  Stephen D. Wyatt

    发明人： Giuseppe La Rosa ,  Kevin Kolvenbach ,  Ping-Chuan Wang ,  Stephen D. Wyatt

    IPC分类号： G01R31/02

    CPC分类号： G01R31/2858 ,  G01R31/2856

    摘要： A method and apparatus for dynamic characterization of reliability wearout mechanisms is disclosed. The system comprises an integrated circuit incorporating a device under test to be measured, structure for inputting a waveform to the device under test for a first predetermined time interval, structure for disabling the inputting of the waveform to the device under test, structure for measuring one or more fundamental parameters of the device under test after a second predetermined time interval, and structure for calculating an aging estimate of the device under test without the influence of recovery effect based on the one or more measured fundamental parameters. The time between stressing and measurement is precisely controlled, providing for repeatable experiments, and serves to minimize measurement error caused by recovery effects.

    摘要翻译： 公开了用于动态表征可靠性损耗机制的方法和装置。 该系统包括结合被测器件的集成电路，用于以第一预定时间间隔向待测器件输入波形的结构，用于禁止向被测器件输入波形的结构，用于测量一个 或更多的基本参数，以及在不受基于一个或多个测量的基本参数的恢复效果的影响下计算被测设备的老化估计的结构。 压力和测量之间的时间被精确控制，提供可重复的实验，并且用于最小化由恢复效果引起的测量误差。

    Circuit and method for on-chip jitter measurement
    23.
    发明授权
    Circuit and method for on-chip jitter measurement 有权
    用于片上抖动测量的电路和方法

    公开(公告)号：US07339364B2

    公开(公告)日：2008-03-04

    申请号：US11424881

    申请日：2006-06-19

    申请人： Brandon R. Kam ,  Stephen D. Wyatt

    发明人： Brandon R. Kam ,  Stephen D. Wyatt

    IPC分类号： G01R23/175 ,  H03L7/06

    CPC分类号： G01R31/31709 ,  G01R29/26 ,  H03L7/07 ,  H03L7/0814

    摘要： An improved built-in self-test (BIST) circuit and an associated method for measuring phase and/or cycle-to-cycle jitter of a clock signal, the BIST circuit implement a Variable Vernier Digital Delay Locked Line method. Specifically, the embodiments of the BIST circuit incorporate both a digital delay locked loop and a Vernier delay line, for respectively coarse tuning and fine tuning portions of the circuit. Additionally, the BIST circuit is variable, as the resolution of the circuit changes from chip to chip, and digital, as it is implemented with standard digital logic elements.

    摘要翻译： 改进的内置自测（BIST）电路和相关方法用于测量时钟信号的相位和/或周期与周期的抖动，BIST电路实现可变游标数字延迟锁定线方法。 具体地，BIST电路的实施例包括数字延迟锁定环和游标延迟线，分别用于电路的粗调和微调部分。 此外，BIST电路是可变的，因为电路的分辨率由芯片变为芯片，而数字是由标准数字逻辑元件实现的。

    Performance measurement of device dedicated to phase locked loop using second order system approximation
    24.
    发明授权
    Performance measurement of device dedicated to phase locked loop using second order system approximation 失效
    使用二阶系统逼近的专用于锁相环的设备的性能测量

    公开(公告)号：US07084615B1

    公开(公告)日：2006-08-01

    申请号：US10906412

    申请日：2005-02-18

    申请人： Faraydon Pakbaz ,  Stephen D. Wyatt

    发明人： Faraydon Pakbaz ,  Stephen D. Wyatt

    IPC分类号： G01R23/12 ,  G01R27/28 ,  G06F17/50

    CPC分类号： G06F17/5036

    摘要： A method, system and program product to measure performance of a device dedicated to a phase locked loop (PLL). A resistor-inductor-capacitor (RLC) model is produced to simulate the PLL. The RLC model and the device to be measured are mapped together into a test circuit and the characteristics of the test circuit is analyzed to determine whether the device, if attached to the PLL represented by the RLC model, can meet the required standard of performance. This invention can be used to measure the performance of all kinds of devices attached to all kinds of PLLs.

    摘要翻译： 用于测量专用于锁相环（PLL）的设备的性能的方法，系统和程序产品。 产生电阻 - 电感 - 电容（RLC）模型来模拟PLL。 将RLC模型和要测量的设备映射到测试电路中，并分析测试电路的特性，以确定如果连接到由RLC模型表示的PLL的设备是否能够满足所需的性能标准。 本发明可用于测量各种类型PLL的各种器件的性能。

    Method and apparatus for reducing jitter in a phase locked loop circuit
    25.
    发明授权
    Method and apparatus for reducing jitter in a phase locked loop circuit 失效
    减少锁相环电路抖动的方法和装置

    公开(公告)号：US5491439A

    公开(公告)日：1996-02-13

    申请号：US298695

    申请日：1994-08-31

    申请人： Ram Kelkar ,  Ilya I Novof ,  Stephen D. Wyatt

    发明人： Ram Kelkar ,  Ilya I Novof ,  Stephen D. Wyatt

    IPC分类号： H03D13/00 ,  H03K3/0231 ,  H03L7/089 ,  H03L7/093 ,  H03L7/095 ,  H03L7/10 ,  H03L7/06

    CPC分类号： H03L7/095 ,  H03K3/0231 ,  H03L7/0893 ,  H03D13/004 ,  H03L2207/06 ,  H03L7/0896 ,  H03L7/0898 ,  Y10S331/02

    摘要： A phase locked loop circuit includes a phase/frequency detector which uses a divider circuit and feedback from a clock distribution tree to generate INC and DEC pulses which have no "dead zone". A pair of charge pumps receives the INC and DEC pulses. One charge pump is a differential pump and has voltage controlled common mode feedback circuit to maintain a common mode controlled voltage. A differential current is outputted to a loop filter capacitor by this charge pump. The other charge pump is a single-ended output pump which supplies current to a current controlled oscillator which also receives input from a voltage to current converter. The current controlled oscillator includes a variable resistance load which varies inversely with the magnitude of the input current. A jitter control circuit is provided which reduces jitter in the current controlled oscillator output in the locked phase. Also, a lock indicator is provided which is time independent, and provides a lock indication when the loop enters the locked condition.

    摘要翻译： 锁相环电路包括相位/频率检测器，该相位/频率检测器使用分频器电路和来自时钟分配树的反馈来产生没有“死区”的INC和DEC脉冲。 一对电荷泵接收INC和DEC脉冲。 一个电荷泵是差分泵，并具有电压控制的共模反馈电路，以保持共模控制电压。 通过该电荷泵将差分电流输出到环路滤波电容器。 另一个电荷泵是一个单端输出泵，它向电流控制振荡器提供电流，该电流控制振荡器也接收电压到电流转换器的输入。 电流控制振荡器包括与输入电流的大小成反比变化的可变电阻负载。 提供了一种抖动控制电路，可减少锁定相中当前受控振荡器输出的抖动。 而且，提供了与时间无关的锁定指示器，并且当环路进入锁定状态时提供锁定指示。

    CIRCUIT AND METHOD FOR ON-CHIP JITTER MEASUREMENT
    26.
    发明申请
    CIRCUIT AND METHOD FOR ON-CHIP JITTER MEASUREMENT 失效
    芯片抖动测量的电路和方法

    公开(公告)号：US20120134403A1

    公开(公告)日：2012-05-31

    申请号：US13364689

    申请日：2012-02-02

    申请人： Brandon R. Kam ,  Stephen D. Wyatt

    发明人： Brandon R. Kam ,  Stephen D. Wyatt

    IPC分类号： H04B17/00

    CPC分类号： G01R31/31709 ,  G01R29/26 ,  H03L7/07 ,  H03L7/0814

    摘要： Disclosed herein are embodiments of an improved built-in self-test (BIST) circuit and an associated method for measuring phase and/or cycle-to-cycle jitter of a clock signal. The embodiments of the BIST circuit implement a Variable Vernier Digital Delay Locked Line method. Specifically, the embodiments of the BIST circuit incorporate both a digital delay locked loop and a Vernier delay line, for respectively coarse tuning and fine tuning portions of the circuit. Additionally, the BIST circuit is variable, as the resolution of the circuit changes from chip to chip, and digital, as it is implemented with standard digital logic elements.

    摘要翻译： 本文公开了改进的内置自测试（BIST）电路和用于测量时钟信号的相位和/或周期到周期抖动的相关方法的实施例。 BIST电路的实施例实现了可变游标数字延迟锁定线方法。 具体地，BIST电路的实施例包括数字延迟锁定环和游标延迟线，分别用于电路的粗调和微调部分。 此外，BIST电路是可变的，因为电路的分辨率由芯片变为芯片，而数字是由标准数字逻辑元件实现的。

    HIGH OUTPUT RESISTANCE, WIDE SWING CHARGE PUMP
    28.
    发明申请
    HIGH OUTPUT RESISTANCE, WIDE SWING CHARGE PUMP 失效
    高输出电阻，宽电流充电泵

    公开(公告)号：US20090033383A1

    公开(公告)日：2009-02-05

    申请号：US11833500

    申请日：2007-08-03

    申请人： Stephen D. Wyatt ,  Tian Xia

    发明人： Stephen D. Wyatt ,  Tian Xia

    IPC分类号： H03L7/08 ,  G05F1/10

    CPC分类号： H03L7/0896 ,  H02M3/07 ,  H03L7/18

    摘要： Disclosed are current sink and source circuits, a charge pump that incorporates them, and a phase locked loop that incorporates the charge pump. The current sink and source circuits each have a current mirror that biases a transistor connected to an output node. These circuits each further have a two-stage feedback amplifier to sense the current mirror drain voltage and to control the transistor gate voltage in order to stabilize the current mirror drain voltage independent of output voltage at the output node. The amplifier also increases output resistance at the output node. This configuration allows for a wide operation voltage range and ensures good circuit performance under a very low power supply. A charge pump that incorporates these circuits generates highly matched charging and discharging currents. A PLL that incorporates this charge pump exhibits minimal bandwidth shifts and minimal locking speed and jitter performance degradation.

    摘要翻译： 公开了当前的电流源和源极电路，它们组合的电荷泵以及结合电荷泵的锁相环。 电流源和电源电路各自具有偏置连接到输出节点的晶体管的电流镜。 这些电路还具有两级反馈放大器以感测电流镜漏极电压并控制晶体管栅极电压，以便稳定电流镜漏极电压，而与输出节点处的输出电压无关。 放大器还增加输出节点的输出电阻。 该配置允许宽的工作电压范围，并在非常低的电源下确保良好的电路性能。 集成这些电路的电荷泵产生高度匹配的充电和放电电流。 集成该电荷泵的PLL具有最小的带宽偏移和最小的锁定速度和抖动性能下降。

    Structure and method for providing gate leakage isolation locally within analog circuits
    29.
    发明授权
    Structure and method for providing gate leakage isolation locally within analog circuits 失效
    在模拟电路中局部提供栅极泄漏隔离的结构和方法

    公开(公告)号：US07268632B2

    公开(公告)日：2007-09-11

    申请号：US11163013

    申请日：2005-09-30

    申请人： Anthony R. Bonaccio ,  Hayden C. Cranford, Jr. ,  Joseph A. Iadanza ,  Stephen D. Wyatt

    发明人： Anthony R. Bonaccio ,  Hayden C. Cranford, Jr. ,  Joseph A. Iadanza ,  Stephen D. Wyatt

    IPC分类号： H03L7/00 ,  H03L7/099 ,  H03B5/18

    CPC分类号： H03L7/093 ,  H03L7/0891

    摘要： A loop filter for a phase-locked-loop is provided, comprising a set of capacitor banks coupled in parallel to form the loop filter, and a detection circuit for identifying and isolating defective capacitor banks. A method for providing a loop filter for a phase-locked-loop in accordance with an embodiment of the present invention includes the steps of forming the loop filter using a set of capacitor banks coupled in parallel, detecting any defective capacitor banks in the set of capacitor banks, isolating each defective capacitor bank, providing a set of redundant capacitor banks, and replacing each defective capacitor bank with a redundant capacitor bank from the set of redundant capacitor banks.

    摘要翻译： 提供了一种用于锁相环的环路滤波器，包括并联耦合以形成环路滤波器的一组电容器组，以及用于识别和隔离有缺陷的电容器组的检测电路。 根据本发明实施例的用于提供用于锁相环的环路滤波器的方法包括以下步骤：使用并联耦合的一组电容器组形成环路滤波器，检测该组中的任何有缺陷的电容器组 电容器组，隔离每个有缺陷的电容器组，提供一组冗余电容器组，并从冗余电容器组组中的冗余电容器组替换每个有缺陷的电容器组。