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公开(公告)号：US09940993B2
公开(公告)日：2018-04-10
申请号：US15093457
申请日：2016-04-07
Applicant: ARM Limited
Inventor： Parameshwarappa Anand Kumar Savanth , James Edward Myers , Pranay Prabhat , David Walter Flynn , Shidhartha Das , David Michael Bull
IPC: G11C5/06 , G11C11/419
CPC classification number: G11C11/419 , G11C5/063 , G11C11/4125
Abstract: A storage bitcell comprising a first inverter cross-coupled with a second inverter, both the first and second inverter being in a path between a first potential and a second potential; wherein a first isolator is connected in the path between the first inverter and the first potential. The storage bitcell has particular application as Static Random-Access Memory (SRAM) circuitry.
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公开(公告)号：US09021298B2
公开(公告)日：2015-04-28
申请号：US14143065
申请日：2013-12-30
Applicant: ARM Limited
Inventor： Shidhartha Das , David Michael Bull , Emre Ozer
IPC: G06F11/00 , G06F11/07 , G01R31/3181 , G06F11/10 , G06F11/16
CPC classification number: G06F11/0793 , G01R31/31816 , G06F11/1076 , G06F11/1608
Abstract: An integrated circuit is provided with error detection circuitry and error repair circuitry. Error tolerance circuitry is responsive to a control parameter to selectively disable the error repair circuitry. The control parameter is dependent on the processing performed within the circuit. For example, the control parameter may be generated in dependence upon the program instruction being executed, the output signal value which is in error, the previous behavior of the circuit or in other ways.
Abstract translation: 集成电路具有错误检测电路和错误修复电路。 误差容限电路响应于控制参数来选择性地禁用错误修复电路。 控制参数取决于电路内执行的处理。 例如，控制参数可以根据执行的程序指令，错误的输出信号值，电路的先前行为或其他方式来生成。
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公开(公告)号：US20250013491A1
公开(公告)日：2025-01-09
申请号：US18706841
申请日：2022-09-28
Applicant: Arm Limited
Inventor： Shidhartha Das , James Edward Myers , Mark John O'Connor
Abstract: A system on chip (102) comprising a plurality of logically homogeneous processor cores (104), each processor core comprising processing circuitry (210) to execute tasks allocated to that processor core, and task scheduling circuitry (202) configured to allocate tasks to the plurality of processor cores. The task scheduling circuitry is configured, for a given task to be allocated, to determine, based on at least one physical circuit implementation property associated with a given processor core, whether the given task is allocated to the given processor core.
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公开(公告)号：US20240162936A1
公开(公告)日：2024-05-16
申请号：US18282899
申请日：2022-02-28
Applicant: Arm Limited , ECS Partners Limited
Inventor： Benjamin James Fletcher , James Edward Myers , Shidhartha Das , Sahan Sajeewa Hiniduma Udugama Gamage
CPC classification number: H04B5/24 , H04L5/0007
Abstract: The present disclosure provides a method and apparatus for communicating between dice of an inductively-coupled 3D integrated circuit (3D-IC). A transmit resonant circuit at a transmit die is inductively coupled to a first receive resonant circuit at a first receive die, and to a second receive resonant circuit at a second receive die. The resonant circuit at the targeted receive die is tuned to the frequency of resonance of the transmit resonant circuit, while the resonant circuit at the untargeted receive die is detuned, resulting in lower power consumption for a given bit error rate at the targeted die.
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25.发明授权公开(公告)号：US11726116B2
公开(公告)日：2023-08-15
申请号：US17218686
申请日：2021-03-31
Applicant: Arm Limited
Inventor： Xiaoqing Xu , Zhiyao Xie , Shidhartha Das
IPC: G01R21/133 , G06F30/3308 , G05F1/66 , G06F30/367 , G01R31/317 , G05B13/02 , G05B15/02 , G06F119/06
CPC classification number: G01R21/133 , G01R31/31727 , G05B13/02 , G05B15/02 , G05F1/66 , G06F30/3308 , G06F30/367 , G06F2119/06
Abstract: An integrated circuit includes a first circuit and a power meter coupled to the first circuit at selected proxy locations. The power meter includes circuitry for generating toggle data, such as signal transitions or signal levels, from signals at the proxy locations and combiner circuitry for combining the toggle data in a first time window with a set of weight value to produce a measure of power usage in the first circuit. The proxy locations and weight values are selected automatically based on simulated or emulated signals from a larger set of locations in the first circuit and associated power usage in the first circuit.
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Patent Agency Ranking
公开(公告)号：US11682432B2
公开(公告)日：2023-06-20
申请号：US17343829
申请日：2021-06-10
Applicant: Arm Limited
Inventor： Supreet Jeloka , Saurabh Pijuskumar Sinha , Shidhartha Das , Mudit Bhargava , Rahul Mathur
Abstract: Various implementations described herein are related to a device having voltage regulation architecture with multiple layers arranged in a multi-layer structure. The device may include one or more layers of the multiple layers with voltage regulation circuitry that may be configured to manage at least one of process variation and temperature variation between the multiple layers of the multi-layer structure.
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27.发明授权公开(公告)号：US11620413B2
公开(公告)日：2023-04-04
申请号：US17048502
申请日：2019-04-18
Applicant: Arm Limited
Inventor： Hugo John Martin Vincent , Shidhartha Das , Milosch Meriac , Vasileios Tenentes
IPC: G06F21/75 , G01R19/165 , G01R31/08 , G06F1/28 , G06F21/44 , H04L9/00 , H04L9/08 , H04L9/32 , G01R19/00 , G01R29/26
Abstract: An apparatus and method for detecting a change in electrical properties in a system is disclosed. Embodiments of the disclosure enable the detection of a change in electrical properties in a system by, in response to a load generated on a power delivery network power in at least part of the system, measuring noise induced in the power delivery network in response to the load. Based on the measured noise, a dynamic-response property of the power delivery network is determined and the dynamic-response property is compared to a stored reference dynamic-response property of the power delivery network based on a predetermined load. In the event of a difference between the dynamic-response property and the reference dynamic-response property, a response to the event is triggered to indicate tampering with the power delivery network.
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公开(公告)号：US11569824B2
公开(公告)日：2023-01-31
申请号：US17344390
申请日：2021-06-10
Applicant: Arm Limited
Inventor： Shidhartha Das , Yunpeng Cai , Supreet Jeloka
Abstract: Various implementations described herein are directed to a device with a voltage-controlled oscillator that receives an enable signal, receives a reset signal, and provides internal pulse signals including one or more coarse internal pulse signals and multiple fine internal pulse signals. The device may have a coarse sampler that receives the one or more coarse internal pulse signal and provides a coarse sampled output signal. The device may have a fine sampler that receives the multiple fine internal pulse signals and provides a fine sampled output signal.
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公开(公告)号：US11423985B2
公开(公告)日：2022-08-23
申请号：US16582743
申请日：2019-09-25
Applicant: Arm Limited
Inventor： Fernando Garcia Redondo , Shidhartha Das , Glen Arnold Rosendale , George McNeil Lattimore , Mudit Bhargava
IPC: G11C13/00
Abstract: In a particular implementation, a method includes: providing a first voltage to a word-line coupled to a first transistor device; providing a second voltage to a bit-line coupled to the first transistor device; providing a third voltage to a source-line coupled between a programmable resistive device and a voltage control element. Also, the first transistor device is coupled to the programmable resistive device and the voltage control element, where the programmable resistive device is configured to replace a first data value by writing a second data value in the programmable resistive device. Moreover, in response to a voltage difference across the programmable resistive device exceeding a particular threshold, limiting the voltage difference by one of reducing the second voltage on the bit-line or increasing the third voltage on the source-line.
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公开(公告)号：US20220199125A1
公开(公告)日：2022-06-23
申请号：US17343829
申请日：2021-06-10
Applicant: Arm Limited
Inventor： Supreet Jeloka , Saurabh Pijuskumar Sinha , Shidhartha Das , Mudit Bhargava , Rahul Mathur
Abstract: Various implementations described herein are related to a device having voltage regulation architecture with multiple layers arranged in a multi-layer structure. The device may include one or more layers of the multiple layers with voltage regulation circuitry that may be configured to manage at least one of process variation and temperature variation between the multiple layers of the multi-layer structure.
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