Integrated circuit with error repair and fault tolerance
    22.
    发明授权
    Integrated circuit with error repair and fault tolerance 有权
    具有错误修复和容错功能的集成电路

    公开(公告)号:US09021298B2

    公开(公告)日:2015-04-28

    申请号:US14143065

    申请日:2013-12-30

    Applicant: ARM Limited

    CPC classification number: G06F11/0793 G01R31/31816 G06F11/1076 G06F11/1608

    Abstract: An integrated circuit is provided with error detection circuitry and error repair circuitry. Error tolerance circuitry is responsive to a control parameter to selectively disable the error repair circuitry. The control parameter is dependent on the processing performed within the circuit. For example, the control parameter may be generated in dependence upon the program instruction being executed, the output signal value which is in error, the previous behavior of the circuit or in other ways.

    Abstract translation: 集成电路具有错误检测电路和错误修复电路。 误差容限电路响应于控制参数来选择性地禁用错误修复电路。 控制参数取决于电路内执行的处理。 例如,控制参数可以根据执行的程序指令,错误的输出信号值,电路的先前行为或其他方式来生成。

    Digital sampling techniques
    28.
    发明授权

    公开(公告)号:US11569824B2

    公开(公告)日:2023-01-31

    申请号:US17344390

    申请日:2021-06-10

    Applicant: Arm Limited

    Abstract: Various implementations described herein are directed to a device with a voltage-controlled oscillator that receives an enable signal, receives a reset signal, and provides internal pulse signals including one or more coarse internal pulse signals and multiple fine internal pulse signals. The device may have a coarse sampler that receives the one or more coarse internal pulse signal and provides a coarse sampled output signal. The device may have a fine sampler that receives the multiple fine internal pulse signals and provides a fine sampled output signal.

    Devices and methods for controlling write operations

    公开(公告)号:US11423985B2

    公开(公告)日:2022-08-23

    申请号:US16582743

    申请日:2019-09-25

    Applicant: Arm Limited

    Abstract: In a particular implementation, a method includes: providing a first voltage to a word-line coupled to a first transistor device; providing a second voltage to a bit-line coupled to the first transistor device; providing a third voltage to a source-line coupled between a programmable resistive device and a voltage control element. Also, the first transistor device is coupled to the programmable resistive device and the voltage control element, where the programmable resistive device is configured to replace a first data value by writing a second data value in the programmable resistive device. Moreover, in response to a voltage difference across the programmable resistive device exceeding a particular threshold, limiting the voltage difference by one of reducing the second voltage on the bit-line or increasing the third voltage on the source-line.

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