公开(公告)号：US4524391A

公开(公告)日：1985-06-18

申请号：US579644

申请日：1984-02-13

申请人： Junichi Nishizawa ,  Takashige Tamamushi ,  Koji Shimanuki ,  Masafumi Inuiya

发明人： Junichi Nishizawa ,  Takashige Tamamushi ,  Koji Shimanuki ,  Masafumi Inuiya

IPC分类号： H01L27/146 ,  H04N5/30 ,  H04N5/335 ,  H04N3/12

CPC分类号： H01L27/14679 ,  H04N5/30

摘要： A two-dimensional solid-state image sensor device comprising a plurality of picture cells two-dimensionally arranged in column and row directions. Each cell has a static induction transistor having drain and source regions disposed on opposite sides of a high resistance semiconductor channel region, and control and shielding gate regions adjacent to the channel region to control a current flowing between the drain and source regions, and a transparent electrode disposed via a capacitance on at least a portion of the control gate region, in a manner that light is incident through the transparent electrode to the control gate region in which the charge produced by the light excitation is stored to control the current. Selection lines and signal readout lines are connected to the control gate regions in each column in common via the capacitances and to the drain or source regions in each row in common, respectively. Each picture cell is selected in the column and row directions so that a signal is read out therefrom.

摘要翻译： 一种二维固态图像传感器装置，其包括在列和行方向上二维布置的多个图像单元。 每个单元具有静电感应晶体管，其具有设置在高电阻半导体沟道区域的相对侧上的漏极和源极区域，以及与沟道区域相邻的控制和屏蔽栅极区域，以控制在漏极和源极区域之间流动的电流，以及透明 电极，其通过在控制栅极区域的至少一部分上的电容设置，使得光通过透明电极入射到控制栅极区域，在该控制栅极区域存储由光激发产生的电荷以控制电流。 选择线和信号读出线分别经由电容和每行中的漏极或源极区域共同地连接到每列中的控制栅极区域。 在列和行方向上选择每个图像单元，从而从其读出信号。

公开(公告)号：US5418376A

公开(公告)日：1995-05-23

申请号：US202821

申请日：1994-02-28

申请人： Kimihiro Muraoka ,  Naohiro Shimizu ,  Takashige Tamamushi

发明人： Kimihiro Muraoka ,  Naohiro Shimizu ,  Takashige Tamamushi

IPC分类号： H01L29/739 ,  H01L29/80

CPC分类号： H01L29/7392

摘要： The present invention is to provide a static induction semiconductor device with a distributed main electrode structure and a static induction semiconductor device with a static induction main electrode shorted structure where the main electrode region is composed of regions of higher and lower impurity densities relative to each other and formed partly in contact with the lower impurity density region as well, and alternatively a static induction short-circuit region opposite in conductivity type to the main electrode region is formed in the lower impurity density region surrounded by the higher impurity density region.

摘要翻译： 本发明提供一种具有分布式主电极结构的静电感应半导体器件和具有静电感应主电极短路结构的静电感应半导体器件，其中主电极区域由相对于彼此的较高和较低杂质浓度的区域组成 并且部分地与下部杂质浓度区域形成接触，或者在由较高杂质浓度区域包围的下部杂质浓度区域中形成与主电极区域相反的导电类型的静电感应短路区域。

公开(公告)号：US4651015A

公开(公告)日：1987-03-17

申请号：US561242

申请日：1983-12-13

申请人： Junichi Nishizawa ,  Takashige Tamamushi

发明人： Junichi Nishizawa ,  Takashige Tamamushi

IPC分类号： H01L29/80 ,  H01L27/146 ,  H04N5/335 ,  H04N5/359 ,  H04N5/369 ,  H04N5/374 ,  H01L27/14 ,  H01L31/00

CPC分类号： H01L27/14679

摘要： A semiconductor imaging device having a wide dynamic range to provide optimum output response characteristics under various illuminating conditions. The device includes a single SIT (Static Induction Transistor) which has a pair of principal electrode regions of one conduction type disposed facing one another through a channel region made of high resistivity semiconductor material. First and second gate regions of the other conduction type are formed in contact with the channel region to control the current flow between the two principal electrode regions. The second gate is common to all pixels. The potential at the second gate region is made variable by a variable power supply, a variable resistor connected between the second gate region and ground, a variable capacitor connected between the second gate region and ground, or combinations of these elements.

摘要翻译： 一种具有宽动态范围的半导体成像装置，以在各种照明条件下提供光电输出响应特性。 该器件包括单个SIT（静态感应晶体管），其具有通过由高电阻率半导体材料制成的沟道区域彼此相对设置的一对导电类型的主电极区域。 另一导电类型的第一和第二栅极区域形成为与沟道区域接触以控制两个主电极区域之间的电流。 第二个门是所有像素共同的。 通过可变电源，连接在第二栅极区域和地之间的可变电阻器，连接在第二栅极区域和地之间的可变电容器，或这些元件的组合，第二栅极区域上的电位可变。

公开(公告)号：US4499654A

公开(公告)日：1985-02-19

申请号：US561120

申请日：1983-12-13

申请人： Junichi Nishizawa ,  Soubei Suzuki ,  Takashige Tamamushi

发明人： Junichi Nishizawa ,  Soubei Suzuki ,  Takashige Tamamushi

IPC分类号： H01L27/146 ,  H01L31/10 ,  H01L21/22 ,  H01L21/265

CPC分类号： H01L27/14692 ,  H01L27/14603 ,  H01L27/14679 ,  H01L27/14687

摘要： A method for forming a semiconductor photodetector array having a matrix of pixels, each constituted by a single SIT (Static Induction Transistor). A field oxide layer is formed on a first main surface of a silicon wafer. Portions of a field oxide layer are then removed from predetermined regions of the first main surface. In these predetermined regions are formed a control gate region and a shielding gate region, with the shielding gate region surrounding the control gate region. Oxide layers are formed on the control gate region and shielding gate region. Portions of the field oxide layer between the control gate region and shielding region are removed to partially expose the first main surface of the silicon wafer, and a first main electrode region is formed in the exposed portion. A first conductive electrode is then deposited on the first main region, whereupon the entirety of the first main surface of the silicon wafer is covered with a first insulating layer. Portions of the first insulating layer are then removed from the control gate region, and the entirety of the first main surface of the silicon wafer is covered with a second insulating layer. A second conductive electrode is then formed on the second insulating layer upon the control gate region. Portions of the first and second insulating layers and the oxide on the shielding gate region are removed to provide a contact hole. The first main surface of the silicon wafer is then covered with a metal layer, portions of which are subsequently removed from the control gate region. Finally, an electrode for the second main electrode region is deposited on the second main surface.

摘要翻译： 一种用于形成具有像素矩阵的半导体光电检测器阵列的方法，每个像素由单个SIT（静态感应晶体管）构成。 在硅晶片的第一主表面上形成场氧化物层。 然后从第一主表面的预定区域去除一部分场氧化物层。 在这些预定区域中形成控制栅极区域和屏蔽栅极区域，屏蔽栅极区域围绕控制栅极区域。 在控制栅极区域和屏蔽栅极区域上形成氧化物层。 除去控制栅极区域和屏蔽区域之间的场氧化物层的一部分以部分地暴露硅晶片的第一主表面，并且在暴露部分中形成第一主电极区域。 然后在第一主区域上沉积第一导电电极，于是硅晶片的第一主表面的整体被第一绝缘层覆盖。 然后从控制栅极区域去除第一绝缘层的部分，并且硅晶片的第一主表面的整体被第二绝缘层覆盖。 然后在控制栅区上在第二绝缘层上形成第二导电电极。 去除第一绝缘层和第二绝缘层的部分和屏蔽栅极区上的氧化物以提供接触孔。 然后用金属层覆盖硅晶片的第一主表面，随后将其部分部分从控制栅极区域移除。 最后，第二主电极区域的电极沉积在第二主表面上。

公开(公告)号：US5545905A

公开(公告)日：1996-08-13

申请号：US229328

申请日：1994-04-18

申请人： Kimihiro Muraoka ,  Naohiro Shimizu ,  Takashige Tamamushi

发明人： Kimihiro Muraoka ,  Naohiro Shimizu ,  Takashige Tamamushi

IPC分类号： H01L29/74 ,  H01L29/739 ,  H01L29/80 ,  H01L27/095 ,  H01L31/112

CPC分类号： H01L29/7392

摘要： The present invention is to provide a Static Induction semiconductor device with a Static Induction Schottky shorted structure where the main electrode region is composed of regions of higher and lower impurity densities relative to each other, the main electrode forms an ohmic contact with the higher impurity density region and also forms a Schottky contact with a Static Induction Schottky shorted region of the lower impurity density region surrounded by tile higher impurity density region, and it is excellent in turn-off performance and easy to use, by substantially reducing tile minority carrier storage time, the fall time and the quantity of gate pull-out charges in order that charges may easily be pulled out from the cathode or source electrode as well as from the gate electrode at turn-off.

摘要翻译： 本发明提供一种具有静态感应肖特基短路结构的静态感应半导体器件，其中主电极区域由相对于彼此的较高和较低杂质浓度的区域组成，主电极形成具有较高杂质密度的欧姆接触 并且还与由较高杂质浓度区域包围的较低杂质浓度区域的静态感应肖特基短路区域形成肖特基接触，并且通过显着减少瓦片少数载流子储存时间，其截止性能优异，易于使用 ，下降时间和栅极引出电荷的量，以便电荷可以容易地从阴极或源极以及关断时从栅电极拉出。

公开(公告)号：US5324966A

公开(公告)日：1994-06-28

申请号：US37023

申请日：1993-03-25

申请人： Kimihiro Muraoka ,  Takashige Tamamushi

发明人： Kimihiro Muraoka ,  Takashige Tamamushi

IPC分类号： H01L29/10 ,  H01L29/745 ,  H01L29/749 ,  H01L29/74

CPC分类号： H01L29/749 ,  H01L29/1016 ,  H01L29/102 ,  H01L29/7455

摘要： The present invention has for its object to provide a planar MOS-controlled thyristor of improved main thyristor turn-ON characteristics and a vertical MOS-controlled thyristor of improved main thyristor turn-ON characteristics and increased integration density. In the planar MOS-controlled thyristor a p-channel MOSFET for turning OFF the main thyristor and an n-channel MOSFET for turning it ON are provided in an integrated form and a channel is provided between the cathode region and a high resistance layer. The current in the channel can be controlled by the base or gate potential through utilization of the J-FET or static induction effect. In the vertical MOS-controlled thyristor a vertical p-channel MOSFET for turning OFF the main thyristor and a vertical n-channel MOSFET for turning it ON are provided in an integrated form and a base layer or channel is provided between the cathode region and a high resistivity layer. The current in the base or channel can be controlled by the base or gate potential through utilization of the base resistance effect, J-FET effect, or static induction effect.

摘要翻译： 本发明的目的是提供一种具有改善的主晶闸管导通特性的平面MOS控制晶闸管和具有改进的主晶闸管导通特性和增加集成密度的垂直MOS控制晶闸管。 在平面MOS控制晶闸管中，用于关断主晶闸管的p沟道MOSFET和用于将其导通的n沟道MOSFET以集成形式提供，并且在阴极区域和高电阻层之间提供沟道。 沟道中的电流可以通过利用J-FET或静态感应效应由基极或栅极电位控制。 在垂直MOS控制的晶闸管中，用于关断主晶闸管的垂直p沟道MOSFET和用于将其导通的垂直n沟道MOSFET以集成形式提供，并且在阴极区域和阴极区域之间提供基极层或沟道 高电阻层。 基极或沟道中的电流可以通过利用基极电阻效应，J-FET效应或静态感应效应的基极或栅极电位来控制。

公开(公告)号：US4725873A

公开(公告)日：1988-02-16

申请号：US882456

申请日：1986-07-08

申请人： Junichi Nishizawa ,  Takashige Tamamushi ,  Sobei Suzuki

发明人： Junichi Nishizawa ,  Takashige Tamamushi ,  Sobei Suzuki

IPC分类号： H01L27/146 ,  H04N5/335 ,  H04N5/359 ,  H01L27/14 ,  H04N3/14

CPC分类号： H01L27/14679

摘要： A semiconductor imaging device composed of a matrix of pixels, each pixel being implemented with a single static induction transistor. Each static induction transistor includes a pair of principal electrode regions disposed facing each other through a highly resistive channel region. First and second gate regions of the conduction type opposite that of the principal electrode regions is formed in contact with the channel region and used to control the current flow between the two principal electrode regions. A capacitor is formed on at least part of the first gate region, whereby carriers generated by light exitation are stored in the first gate region. The second gate region is formed surrounding the first gate region and is common to all pixels. This construction provides a high-level output signal and good isolation between pixels, with an attendant increase in blooming resistance.

摘要翻译： 由像素矩阵构成的半导体成像装置，每个像素由单个静态感应晶体管实现。 每个静态感应晶体管包括通过高电阻沟道区域彼此相对设置的一对主电极区域。 与主电极区域相反的导电类型的第一和第二栅极区域形成为与沟道区域接触，并用于控制两个主电极区域之间的电流。 在第一栅极区域的至少一部分上形成电容器，由此由光照射产生的载流子存储在第一栅极区域中。 第二栅极区域围绕第一栅极区域形成，并且对于所有像素是共同的。 这种结构提供了高电平输出信号和像素之间的良好隔离，伴随着起霜电阻的增加。

公开(公告)号：US4502203A

公开(公告)日：1985-03-05

申请号：US561243

申请日：1983-12-13

申请人： Junichi Nishizawa ,  Soubei Suzuki ,  Takashige Tamamushi

发明人： Junichi Nishizawa ,  Soubei Suzuki ,  Takashige Tamamushi

IPC分类号： H01L27/146 ,  H01L31/10 ,  H01L21/22

CPC分类号： H01L27/14603 ,  H01L27/14623 ,  H01L27/14679 ,  H01L27/14687

摘要： A method for fabricating a photodetector device including a single pixel or an array of pixels, each of which is constituted by a single vertical type SIT (Static Induction Transistor). First and second main electrode regions are formed on respective first and second main surfaces of a silicon wafer. Control gate and shielding gate regions, as well as drain and source regions as well, are formed using a single common masking step. As a result, the formation of these regions is precisely controlled, resulting in superior photoresponse characteristics.

摘要翻译： 一种用于制造包括单个像素或像素阵列的光电检测器件的方法，每个像素由单个垂直型SIT（静态感应晶体管）构成。 第一和第二主电极区域形成在硅晶片的相应的第一和第二主表面上。 控制栅极和屏蔽栅极区以及漏极和源极区也使用单个公共掩模步骤形成。 结果，这些区域的形成被精确地控制，导致优异的光响应特性。

公开(公告)号：US5682044A

公开(公告)日：1997-10-28

申请号：US591420

申请日：1996-01-19

申请人： Takashige Tamamushi ,  Kimihiro Muraoka ,  Yoshiaki Ikeda ,  Keun Sam Lee ,  Naohiro Shimizu ,  Masashi Yura ,  Kinji Yoshioka

发明人： Takashige Tamamushi ,  Kimihiro Muraoka ,  Yoshiaki Ikeda ,  Keun Sam Lee ,  Naohiro Shimizu ,  Masashi Yura ,  Kinji Yoshioka

IPC分类号： H01L29/74 ,  H01L31/111

CPC分类号： H01L29/7416

摘要： The present invention provides a reverse conducting (RC) thyristor of a planar-gate structure for low-and-medium power use which is relatively simple in construction because of employing a planar structure for each of thyristor and diode regions, permits simultaneous formation of the both region and have high-speed performance and a RC thyristor of a buried-gate or recessed-gate structure which has a high breakdown voltage by the use of a buried-gate or recessed-gate structure, permits simultaneous formation of thyristor and diode regions and high-speed, high current switching performance, and the RC thyristor of the planar-gate structure has a construction which comprises an SI thyristor or miniaturized GTO of a planar-gate structure in the thyristor region and an SI diode of a planar structure in the diode region, the diode region having at its cathode side a Schottky contact between n emitters or diode cathode shorted region and the thyristor region having at its anode side an SI anode shorted structure formed by p.sup.+ anode layers, wave-shaped anode layers or anode n.sup.+ layers; in the case of a high breakdown device, an n buffer layer is added; similarly the RC thyristor of the buried-gate or recessed-gate structure has a construction which comprises an SI thyristor of a buried-gate or recessed-gate structure at the thyristor region and an SI diode of the buried or recessed structure.

摘要翻译： 本发明提供了一种用于中低功率使用的平面栅极结构的反向导通（RC）晶闸管，由于采用晶体管和二极管区域中的每一个的平面结构，其结构相对简单，允许同时形成 具有高速性能和通过使用掩埋栅极或凹入栅极结构具有高击穿电压的掩埋栅极或凹入栅极结构的RC晶闸管，允许同时形成晶闸管和二极管区域 和高速，高电流开关性能，并且平面栅极结构的RC晶闸管具有在晶闸管区域中包括SI晶闸管或平面栅极结构的小型化GTO以及平面结构的SI二极管的结构 二极管区域，二极管区域在其阴极侧具有n个发射极或二极管阴极短路区域之间的肖特基接触，并且在其阳极侧具有SI a的晶闸管区域 由p +阳极层，波形阳极层或阳极n +层形成的短路结构; 在高击穿装置的情况下，添加n缓冲层; 类似地，埋入栅极或凹入栅极结构的RC晶闸管具有包括在晶闸管区域处的掩埋栅极或凹入栅极结构的SI晶闸管和埋入或凹陷结构的SI二极管的结构。

公开(公告)号：US5665987A

公开(公告)日：1997-09-09

申请号：US414346

申请日：1995-03-31

申请人： Kimihiro Muraoka ,  Yoshinobu Ohtsubo ,  Toshio Higuchi ,  Makoto Iguchi ,  Takashige Tamamushi

发明人： Kimihiro Muraoka ,  Yoshinobu Ohtsubo ,  Toshio Higuchi ,  Makoto Iguchi ,  Takashige Tamamushi

IPC分类号： H01L29/74 ,  H01L29/739 ,  H01L29/749 ,  H01L31/111

CPC分类号： H01L29/7392

摘要： In a gate insulated static induction thyristor with a split gate type shorted cathode structure, a first gate of the split gate structure is used as a cathode short-circuit gate and the cathode region is formed in the second gate. A MOS structure is formed on the second gate as a control gate electrode isolated therefrom. Since the channel integration density is high, the area efficiency increases. The MOS gate structure suppresses the minority carrier (hole) storage effect to permit high-speed swtching of the thyristor, and the shorted cathode structure provides for increased maximum controllable current/voltage durability. The split gate structure can be used in combination with planar, buried, recessed and double gate structures.

摘要翻译： 在具有分裂栅型短路阴极结构的栅极绝缘静电感应晶闸管中，分离栅极结构的第一栅极用作阴极短路栅极，阴极区域形成在第二栅极中。 在第二栅极上形成作为与其隔离的控制栅电极的MOS结构。 由于通道集成密度高，面积效率提高。 MOS栅极结构抑制了少量载流子（空穴）储存效应，从而允许晶闸管高速切换，短路阴极结构提供了最大可控电流/电压耐久性。 分裂栅极结构可以与平面，埋入，凹陷和双栅结构结合使用。