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1.发明授权Static induction semiconductor device with a distributed main electrode structure and static induction semiconductor device with a static induction main electrode shorted structure 失效静电感应半导体器件具有分布式主电极结构和静电感应半导体器件，具有静电感应主电极短路结构
公开(公告)号：US5418376A
公开(公告)日：1995-05-23
申请号：US202821
申请日：1994-02-28
IPC分类号： H01L29/739 , H01L29/80
CPC分类号： H01L29/7392
摘要： The present invention is to provide a static induction semiconductor device with a distributed main electrode structure and a static induction semiconductor device with a static induction main electrode shorted structure where the main electrode region is composed of regions of higher and lower impurity densities relative to each other and formed partly in contact with the lower impurity density region as well, and alternatively a static induction short-circuit region opposite in conductivity type to the main electrode region is formed in the lower impurity density region surrounded by the higher impurity density region.
摘要翻译： 本发明提供一种具有分布式主电极结构的静电感应半导体器件和具有静电感应主电极短路结构的静电感应半导体器件，其中主电极区域由相对于彼此的较高和较低杂质浓度的区域组成 并且部分地与下部杂质浓度区域形成接触，或者在由较高杂质浓度区域包围的下部杂质浓度区域中形成与主电极区域相反的导电类型的静电感应短路区域。
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2.发明授权Static induction semiconductor device with a static induction schottky shorted structure 失效具有静态感应肖特基短路结构的静态感应半导体器件
公开(公告)号：US5545905A
公开(公告)日：1996-08-13
申请号：US229328
申请日：1994-04-18
IPC分类号： H01L29/74 , H01L29/739 , H01L29/80 , H01L27/095 , H01L31/112
CPC分类号： H01L29/7392
摘要： The present invention is to provide a Static Induction semiconductor device with a Static Induction Schottky shorted structure where the main electrode region is composed of regions of higher and lower impurity densities relative to each other, the main electrode forms an ohmic contact with the higher impurity density region and also forms a Schottky contact with a Static Induction Schottky shorted region of the lower impurity density region surrounded by tile higher impurity density region, and it is excellent in turn-off performance and easy to use, by substantially reducing tile minority carrier storage time, the fall time and the quantity of gate pull-out charges in order that charges may easily be pulled out from the cathode or source electrode as well as from the gate electrode at turn-off.
摘要翻译： 本发明提供一种具有静态感应肖特基短路结构的静态感应半导体器件，其中主电极区域由相对于彼此的较高和较低杂质浓度的区域组成，主电极形成具有较高杂质密度的欧姆接触 并且还与由较高杂质浓度区域包围的较低杂质浓度区域的静态感应肖特基短路区域形成肖特基接触，并且通过显着减少瓦片少数载流子储存时间，其截止性能优异，易于使用 ，下降时间和栅极引出电荷的量，以便电荷可以容易地从阴极或源极以及关断时从栅电极拉出。
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3.发明授权Reverse conducting thyristor with a planar-gate, buried-gate, or recessed-gate structure 失效具有平面栅极，掩埋栅极或凹入栅极结构的反向导通晶闸管
公开(公告)号：US5682044A
公开(公告)日：1997-10-28
申请号：US591420
申请日：1996-01-19
申请人： Takashige Tamamushi , Kimihiro Muraoka , Yoshiaki Ikeda , Keun Sam Lee , Naohiro Shimizu , Masashi Yura , Kinji Yoshioka
发明人： Takashige Tamamushi , Kimihiro Muraoka , Yoshiaki Ikeda , Keun Sam Lee , Naohiro Shimizu , Masashi Yura , Kinji Yoshioka
IPC分类号： H01L29/74 , H01L31/111
CPC分类号： H01L29/7416
摘要： The present invention provides a reverse conducting (RC) thyristor of a planar-gate structure for low-and-medium power use which is relatively simple in construction because of employing a planar structure for each of thyristor and diode regions, permits simultaneous formation of the both region and have high-speed performance and a RC thyristor of a buried-gate or recessed-gate structure which has a high breakdown voltage by the use of a buried-gate or recessed-gate structure, permits simultaneous formation of thyristor and diode regions and high-speed, high current switching performance, and the RC thyristor of the planar-gate structure has a construction which comprises an SI thyristor or miniaturized GTO of a planar-gate structure in the thyristor region and an SI diode of a planar structure in the diode region, the diode region having at its cathode side a Schottky contact between n emitters or diode cathode shorted region and the thyristor region having at its anode side an SI anode shorted structure formed by p.sup.+ anode layers, wave-shaped anode layers or anode n.sup.+ layers; in the case of a high breakdown device, an n buffer layer is added; similarly the RC thyristor of the buried-gate or recessed-gate structure has a construction which comprises an SI thyristor of a buried-gate or recessed-gate structure at the thyristor region and an SI diode of the buried or recessed structure.
摘要翻译： 本发明提供了一种用于中低功率使用的平面栅极结构的反向导通（RC）晶闸管，由于采用晶体管和二极管区域中的每一个的平面结构，其结构相对简单，允许同时形成 具有高速性能和通过使用掩埋栅极或凹入栅极结构具有高击穿电压的掩埋栅极或凹入栅极结构的RC晶闸管，允许同时形成晶闸管和二极管区域 和高速，高电流开关性能，并且平面栅极结构的RC晶闸管具有在晶闸管区域中包括SI晶闸管或平面栅极结构的小型化GTO以及平面结构的SI二极管的结构 二极管区域，二极管区域在其阴极侧具有n个发射极或二极管阴极短路区域之间的肖特基接触，并且在其阳极侧具有SI a的晶闸管区域 由p +阳极层，波形阳极层或阳极n +层形成的短路结构; 在高击穿装置的情况下，添加n缓冲层; 类似地，埋入栅极或凹入栅极结构的RC晶闸管具有包括在晶闸管区域处的掩埋栅极或凹入栅极结构的SI晶闸管和埋入或凹陷结构的SI二极管的结构。
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公开(公告)号：US5352910A
公开(公告)日：1994-10-04
申请号：US42152
申请日：1993-04-02
IPC分类号： H01L29/08 , H01L29/739 , H01L29/74
CPC分类号： H01L29/0834 , H01L29/7392
摘要： The present invention is directed to power semiconductor devices and, more particularly, to a semiconductor device with a static induction buffer structure which reduces the resistance of a buffer layer, enhances the injection efficiency of holes from the anode and permits the application of a high-intensity electric field across the cathode and anode, and a semiconductor device with a drift buffer structure in which an impurity density (concentration) gradient is set in a buffer layer to generate an internal electric field for holes to enhance the injection efficiency of holes from the anode and increase the electron storage efficiency or and impurity density (concentration) gradient is set in an anode region to generate an internal electric field for electrons and a high-intensity electric field can be applied across the cathode and anode.
摘要翻译： 本发明涉及功率半导体器件，更具体地说，涉及具有降低缓冲层电阻的静态感应缓冲结构的半导体器件，增强了来自阳极的孔的注入效率， 阴极和阳极两端的强度电场，以及具有漂移缓冲结构的半导体器件，其中在缓冲层中设置杂质浓度（浓度）梯度以产生用于孔的内部电场，以提高孔的注入效率 阳极并增加电子存储效率，并且在阳极区域中设置杂质浓度（浓度）梯度以产生用于电子的内部电场，并且可以在阴极和阳极之间施加高强度电场。
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公开(公告)号：US5324966A
公开(公告)日：1994-06-28
申请号：US37023
申请日：1993-03-25
IPC分类号： H01L29/10 , H01L29/745 , H01L29/749 , H01L29/74
CPC分类号： H01L29/749 , H01L29/1016 , H01L29/102 , H01L29/7455
摘要： The present invention has for its object to provide a planar MOS-controlled thyristor of improved main thyristor turn-ON characteristics and a vertical MOS-controlled thyristor of improved main thyristor turn-ON characteristics and increased integration density. In the planar MOS-controlled thyristor a p-channel MOSFET for turning OFF the main thyristor and an n-channel MOSFET for turning it ON are provided in an integrated form and a channel is provided between the cathode region and a high resistance layer. The current in the channel can be controlled by the base or gate potential through utilization of the J-FET or static induction effect. In the vertical MOS-controlled thyristor a vertical p-channel MOSFET for turning OFF the main thyristor and a vertical n-channel MOSFET for turning it ON are provided in an integrated form and a base layer or channel is provided between the cathode region and a high resistivity layer. The current in the base or channel can be controlled by the base or gate potential through utilization of the base resistance effect, J-FET effect, or static induction effect.
摘要翻译： 本发明的目的是提供一种具有改善的主晶闸管导通特性的平面MOS控制晶闸管和具有改进的主晶闸管导通特性和增加集成密度的垂直MOS控制晶闸管。 在平面MOS控制晶闸管中，用于关断主晶闸管的p沟道MOSFET和用于将其导通的n沟道MOSFET以集成形式提供，并且在阴极区域和高电阻层之间提供沟道。 沟道中的电流可以通过利用J-FET或静态感应效应由基极或栅极电位控制。 在垂直MOS控制的晶闸管中，用于关断主晶闸管的垂直p沟道MOSFET和用于将其导通的垂直n沟道MOSFET以集成形式提供，并且在阴极区域和阴极区域之间提供基极层或沟道 高电阻层。 基极或沟道中的电流可以通过利用基极电阻效应，J-FET效应或静态感应效应的基极或栅极电位来控制。
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6.发明授权Insulated gate static induction thyristor with a split gate type shorted cathode structure 失效绝缘栅静电感应晶闸管采用裂缝型短路阴极结构
公开(公告)号：US5665987A
公开(公告)日：1997-09-09
申请号：US414346
申请日：1995-03-31
IPC分类号： H01L29/74 , H01L29/739 , H01L29/749 , H01L31/111
CPC分类号： H01L29/7392
摘要： In a gate insulated static induction thyristor with a split gate type shorted cathode structure, a first gate of the split gate structure is used as a cathode short-circuit gate and the cathode region is formed in the second gate. A MOS structure is formed on the second gate as a control gate electrode isolated therefrom. Since the channel integration density is high, the area efficiency increases. The MOS gate structure suppresses the minority carrier (hole) storage effect to permit high-speed swtching of the thyristor, and the shorted cathode structure provides for increased maximum controllable current/voltage durability. The split gate structure can be used in combination with planar, buried, recessed and double gate structures.
摘要翻译： 在具有分裂栅型短路阴极结构的栅极绝缘静电感应晶闸管中，分离栅极结构的第一栅极用作阴极短路栅极，阴极区域形成在第二栅极中。 在第二栅极上形成作为与其隔离的控制栅电极的MOS结构。 由于通道集成密度高，面积效率提高。 MOS栅极结构抑制了少量载流子（空穴）储存效应，从而允许晶闸管高速切换，短路阴极结构提供了最大可控电流/电压耐久性。 分裂栅极结构可以与平面，埋入，凹陷和双栅结构结合使用。
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7.发明授权Insulated gate static induction thyristor with a split gate type shorted cathode structure 失效绝缘栅静电感应晶闸管采用裂缝型短路阴极结构
公开(公告)号：US5461242A
公开(公告)日：1995-10-24
申请号：US145436
申请日：1993-10-29
IPC分类号： H01L29/74 , H01L29/739 , H01L29/749
CPC分类号： H01L29/7391 , H01L29/7392
摘要： In a gate insulated static induction thyristor with a split gate type shorted cathode structure, a first gate region of the split gate structure is used as a cathode short-circuit gate and the cathode region is formed between the first and second gate regions. A MOS structure is formed on the second gate region as a insulated gate control gate region electrode isolated therefrom. The MOS gate structure suppresses the minority carrier (hole) storage effect to permit high-speed switching of the thyristor, and the shorted cathode structure provides for increased maximum controllable current/voltage durability. The split gate structure can be used in combination with planar, buried, recessed and double gate structures.
摘要翻译： 在具有分裂栅型短路阴极结构的栅极绝缘静电感应晶闸管中，分离栅极结构的第一栅极区域用作阴极短路栅极，并且阴极区域形成在第一和第二栅极区域之间。 在第二栅极区域形成MOS结构，作为与其隔离的绝缘栅极控制栅极区域电极。 MOS栅极结构抑制了少量载流子（空穴）储存效应，从而允许晶闸管高速切换，短路阴极结构提供了最大可控电流/电压耐久性。 分裂栅极结构可以与平面，埋入，凹陷和双栅结构结合使用。
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8.发明授权Method for the formation of buried gates of a semiconductor device utilizing etch and refill techniques 失效利用蚀刻和再填充技术形成半导体器件的掩埋栅极的方法
公开(公告)号：US4528745A
公开(公告)日：1985-07-16
申请号：US511193
申请日：1983-07-06
申请人： Kimihiro Muraoka
发明人： Kimihiro Muraoka
IPC分类号： H01L21/20 , H01L21/225 , H01L21/28 , H01L21/335 , H01L29/10 , H01L21/74
CPC分类号： H01L29/66416 , H01L21/02381 , H01L21/0243 , H01L21/02532 , H01L21/02639 , H01L21/2257 , H01L21/28 , H01L29/102 , H01L29/1066 , Y10S148/037 , Y10S148/039 , Y10S148/05 , Y10S148/088
摘要： A method for the formation of buried gates in a semiconductor device using epitaxial growing method combined with diffusion method or diffusion by an additional heat treatment. The buried gate has smaller gate resistance by providing relatively high impurity concentration and also having good reverse characteristic by providing relatively low impurity concentration at the top of the buried gates.
摘要翻译： 一种使用外延生长方法结合扩散方法或通过附加热处理扩散的半导体器件中形成掩埋栅极的方法。 通过提供相对高的杂质浓度并且通过在掩埋栅极的顶部提供较低的杂质浓度具有良好的反向特性，掩埋栅极具有较小的栅极电阻。
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公开(公告)号：US4654679A
公开(公告)日：1987-03-31
申请号：US656581
申请日：1984-10-01
申请人： Kimihiro Muraoka
发明人： Kimihiro Muraoka
IPC分类号： H01L29/08 , H01L29/10 , H01L29/739 , H01L29/80
CPC分类号： H01L29/0843 , H01L29/0834 , H01L29/1066 , H01L29/7392
摘要： A static induction thyristor having buried gate region having the concentration distribution of the impurity to have at least one stepwise variation viewed from the surface of the gate for improving dv/dt capability and for allowing more tolerance in the accuracy in the over-etching and also for keeping variation of the gate resistance small. A static induction thyristor having buried gate region and having the high concentration layer given selective junction depth and to make shallow for the location situated above or below the gate region and may be provided with insulating layer between anode or cathode electrode for further improving dv/dt capability and also the gate loss at turn-on in high frequency operation and for improving manufacturing yield.
摘要翻译： 具有掩模栅极区域的静态感应晶闸管具有从栅极表面观察到的具有至少一个逐步变化的杂质的浓度分布，以提高dv / dt能力，并允许在过蚀刻中的精度更多的公差 用于保持栅极电阻变化小。 具有掩埋栅极区域并具有选择性结深度的高浓度层的静态感应晶闸管，并且对于位于栅极区域上方或下方的位置使其较浅，并且可以在阳极或阴极之间设置绝缘层，以进一步改善dv / dt 能力以及在高频操作中接通时的栅极损耗以及提高制造产量。
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