公开(公告)号：US06882182B1

公开(公告)日：2005-04-19

申请号：US10669589

申请日：2003-09-23

申请人： Robert O. Conn ,  Gary R. Lawman ,  Christopher H. Kingsley ,  Austin H. Lesea

发明人： Robert O. Conn ,  Gary R. Lawman ,  Christopher H. Kingsley ,  Austin H. Lesea

IPC分类号： G06F1/10 ,  H03K3/012 ,  H03K19/00

CPC分类号： G06F1/10 ,  H03K3/012

摘要： A tunable clock distribution system is used to minimize the power dissipation of a clock distribution network in an integrated circuit. The tunable clock distribution system provides a tunable inductance on the clock distribution network to adjust a resonant frequency in the tunable clock distribution system. The inductance is tuned so that the resonant frequency of the tunable clock distribution system approaches the frequency of the clock signal on the clock distribution network. As the resonant frequency of the tunable clock distribution system approaches the frequency of the clock signal, the power dissipation of the clock distribution network decreases. Some embodiments also provide a tunable capacitance on the clock distribution network to adjust the resonant frequency of the tunable clock distribution system.

摘要翻译： 可调谐时钟分配系统用于最小化集成电路中时钟分配网络的功耗。 可调时钟分配系统在时钟分配网络上提供可调电感，以调节可调时钟分配系统中的谐振频率。 调谐电感使得可调谐时钟分配系统的谐振频率接近时钟分配网络上时钟信号的频率。 随着可调谐时钟分配系统的谐振频率接近时钟信号的频率，时钟分配网络的功耗降低。 一些实施例还在时钟分配网络上提供可调谐电容以调节可调时钟分配系统的谐振频率。

公开(公告)号：US06874107B2

公开(公告)日：2005-03-29

申请号：US09912683

申请日：2001-07-24

申请人： Austin H. Lesea

发明人： Austin H. Lesea

IPC分类号： G01R31/28 ,  G01R31/317 ,  G01R31/3183 ,  G06F11/00 ,  G06F11/22 ,  H01L21/822 ,  H01L27/04 ,  H03K19/173 ,  G01R31/3185 ,  G06F17/50 ,  H01L25/00 ,  H03M9/00 ,  H01K19/177

CPC分类号： G01R31/31701 ,  G01R31/31715 ,  G01R31/318342

摘要： A field programmable gate array (FPGA) device includes a high-speed serializer/deserializer (SERDES). The field programmable gate array allows programmable built-in testing of the SERDES at operating speeds. A digital clock manager circuit allows clock signals coupled to the SERDES to be modified during the test operations to stress the SERDES circuit. The logic array of the FPGA can be programmed to generate test patterns and to analyze data received by the SERDES circuit. Cyclic redundancy check (CRC) characters, or other error checking characters, can also be generated using the logic array. During testing, the FPGA can perform extensive tests on the communication circuitry and store the results of the testing. An external tester can read the results of the test without substantial test time or complicated test equipment. After testing is complete, the device may be re-programmed to perform the end-user function, adding zero cost to the device for test implementation.

摘要翻译： 现场可编程门阵列（FPGA）装置包括高速串行器/解串器（SERDES）。 现场可编程门阵列允许在运行速度下对SERDES进行可编程的内置测试。 数字时钟管理器电路允许在测试操作期间耦合到SERDES的时钟信号被修改以对SERDES电路施加压力。 可以对FPGA的逻辑阵列进行编程，以生成测试模式并分析由SERDES电路接收的数据。 循环冗余校验（CRC）字符或其他错误检查字符也可以使用逻辑阵列生成。 在测试期间，FPGA可以对通信电路进行大量测试，并存储测试结果。 外部测试仪可以在没有实质测试时间或复杂的测试设备的情况下读取测试结果。 测试完成后，设备可能被重新编程为执行最终用户功能，为设备添加零成本用于测试实现。

公开(公告)号：US06836168B1

公开(公告)日：2004-12-28

申请号：US10264204

申请日：2002-10-02

申请人： Austin H. Lesea ,  Atul V. Ghia

发明人： Austin H. Lesea ,  Atul V. Ghia

IPC分类号： H03K512

CPC分类号： H03K17/167 ,  H03K5/04 ,  H03K2005/00019

摘要： A line driver with programmable slew rates is disclosed. The line driver can be configured to have a slew rate based on a desired fraction of the clock period of the system clock. Specifically, the clock period of the system clock signal is equal to a clock period reference number multiplied by a base delay. A number of base delays is calculated to be equal to the desired fraction of the clock period multiplied by the clock period reference number. The slew rate of the line driver is adjusted to be equal to the number of base delays.

摘要翻译： 公开了一种具有可编程转换速率的线路驱动器。 线路驱动器可以被配置为具有基于系统时钟的时钟周期的期望分数的压摆率。 具体地说，系统时钟信号的时钟周期等于时钟周期参考数乘以基本延迟。 计算多个基本延迟时间等于时钟周期的期望分数乘以时钟周期参考号。 线路驱动器的转换速率被调整为等于基本延迟的数量。

公开(公告)号：US06809957B2

公开(公告)日：2004-10-26

申请号：US10787331

申请日：2004-02-26

申请人： Austin H. Lesea

发明人： Austin H. Lesea

IPC分类号： G11C1100

CPC分类号： G11C11/4125

摘要： Method and apparatus are described for providing memory cells enhanced for resistance to single event upsets. In one embodiment, transistors are coupled between cross coupled inverters of a latch, thus in a small area providing both single-event-upset resistivity most of the time, and high speed during writing to the memory cell. Alternatively, inductors coupled between inverters of a latch may be used.

摘要翻译： 描述了用于提供增强以抵抗单事件扰乱的存储单元的方法和装置。 在一个实施例中，晶体管耦合在锁存器的交叉耦合的反相器之间，因此在大部分时间内提供单事件不稳定电阻的小区域以及写入存储器单元期间的高速度。 或者，可以使用耦合在锁存器的反相器之间的电感器。

公开(公告)号：US06275191B1

公开(公告)日：2001-08-14

申请号：US09634698

申请日：2000-08-08

申请人： Austin H. Lesea ,  Robert O. Conn

发明人： Austin H. Lesea ,  Robert O. Conn

IPC分类号： H01Q138

CPC分类号： H01Q21/0037 ,  H01Q1/38

摘要： The maximum propagation speed of an electrical signal travelling on a conductor in an integrated circuit is limited by the dielectric constant of the dielectric material surrounding the conductor. Rather than transmitting an electrical signal through a conductor that is surrounded with a dielectric material having a dielectric constant of two or more, the signal is propagated as an electromagnetic wave through air at a much higher speed across the surface of the integrated circuit. In one embodiment, a radio frequency (RF) signal is passed into an integrated circuit package via a transmission line. The transmission line supplies the RF signal to a waveguide-like structure disposed above the integrated circuit inside the package. The RF signal propagates as an electromagnetic wave through air in the waveguide structure across the upper surface of the integrated circuit. Antenna/receiver circuit pairs are disposed at various locations across the surface of the integrated circuit where the signal is to be received and used. Other methods and embodiments are disclosed.

公开(公告)号：US4633040A

公开(公告)日：1986-12-30

申请号：US664774

申请日：1984-10-25

申请人： Austin H. Lesea

发明人： Austin H. Lesea

IPC分类号： H04M1/82 ,  H04M7/00 ,  H04M3/02 ,  H04M3/22

CPC分类号： H04M7/0096 ,  H04M1/82

摘要： A personal branch exchange telephone system including improved interface circuitry to couple the system to outside telephone lines as well as to individual telephone sets on extension lines in the PBX system. The PBX system is connected to the telephone lines only through electromagnetic coupling and circuitry is provided to detect both ringing signals and loop current carried by the telephone lines.

摘要翻译： 一种个人分支交换电话系统，包括改进的接口电路，以将系统耦合到外部电话线以及PBX系统中延长线上的各个电话机。 PBX系统仅通过电磁耦合连接到电话线，并提供电路以检测电话线路携带的振铃信号和回路电流。

公开(公告)号：US09003221B1

公开(公告)日：2015-04-07

申请号：US13438814

申请日：2012-04-03

申请人： Khaldoon S. Abugharbieh ,  Daniel J. Ferris, III ,  Loren Jones ,  Austin H. Lesea

发明人： Khaldoon S. Abugharbieh ,  Daniel J. Ferris, III ,  Loren Jones ,  Austin H. Lesea

IPC分类号： G06F11/00 ,  G06F11/32

CPC分类号： G06F11/323 ,  G01R31/31725 ,  G01R31/318513 ,  G06F1/10

摘要： An embodiment for skew compensation for a stacked die is disclosed. For an embodiment of an apparatus, an interposer has a first and a second integrated circuit die coupled to the interposer. The first integrated circuit die includes an information generator, a signal delay compensator, and an input/output block. The information generator is configured to determine: a first delay value for a first path of the interposer between the first integrated circuit die and the second integrated circuit die; a second delay value for a second path of the interposer between the first integrated circuit die and the second integrated circuit die; and a difference between the first delay value and the second delay value. The signal delay compensator is coupled to receive the difference and configured to adjust a parameter of the first integrated circuit die to reduce the difference.

摘要翻译： 公开了一种用于堆叠管芯的偏斜补偿的实施例。 对于装置的实施例，插入器具有耦合到插入器的第一和第二集成电路管芯。 第一集成电路管芯包括信息发生器，信号延迟补偿器和输入/输出块。 信息发生器被配置为确定：第一集成电路管芯和第二集成电路管芯之间的插入件的第一路径的第一延迟值; 所述第一集成电路管芯和所述第二集成电路管芯之间的所述插入件的第二路径的第二延迟值; 以及第一延迟值和第二延迟值之间的差。 信号延迟补偿器被耦合以接收差分并被配置为调整第一集成电路管芯的参数以减小差异。

公开(公告)号：US08375338B1

公开(公告)日：2013-02-12

申请号：US12975102

申请日：2010-12-21

申请人： Jameel Hussein ,  Austin H. Lesea ,  Kenneth D. Chapman ,  Ching Y. Hu

发明人： Jameel Hussein ,  Austin H. Lesea ,  Kenneth D. Chapman ,  Ching Y. Hu

IPC分类号： G06F17/50

CPC分类号： G06F17/5022 ,  G06F17/5036 ,  G06F2217/76 ,  G06F2217/82

摘要： Methods and systems estimate a rate of corruption of storage bits in a logic circuit. One or more processors execute instructions that cause the processors to perform the operations that follow. A description is input describing an environment of the logic circuit, and the description of the environment includes a position of the logic circuit. An atomic particle flux density at the logic circuit is estimated as a function of the description of the environment. A specification is input that specifies the storage bits in the logic circuit. The rate of corruption of the storage bits is determined as a function of the atomic particle flux density and a quantification of the storage bits in the logic circuit.

摘要翻译： 方法和系统估计逻辑电路中存储位的损坏率。 一个或多个处理器执行使处理器执行随后的操作的指令。 描述逻辑电路的环境的描述，并且环境的描述包括逻辑电路的位置。 逻辑电路上的原子粒子通量密度被估计为对环境的描述的函数。 一个规范是指定逻辑电路中的存储位的输入。 存储位的损坏率被确定为原子粒子通量密度和逻辑电路中的存储位的量化的函数。

公开(公告)号：US07852108B1

公开(公告)日：2010-12-14

申请号：US12715230

申请日：2010-03-01

申请人： Austin H. Lesea

发明人： Austin H. Lesea

IPC分类号： H03K19/003

CPC分类号： H03K19/17704 ,  H03K3/356121 ,  H03K19/00338 ,  H03K19/17736 ,  H03K19/1776 ,  H03K19/17764 ,  H03K19/1778

摘要： In one embodiment of the present invention, a programmable interconnect circuit is provided. The programmable interconnect circuit includes first and second static random access memory cells, each having a first output and a second output. The second output is an inversion of the first output. First and second pass gates are each coupled to one of the first and second outputs of the respective first and second memory cells. First and second lock-state circuits are coupled to the respective first and second memory cells. In response to a configuration status signal and the first output of one of the memory cells being asserted to a low voltage, the respective lock-state circuit is configured to maintain the one of the outputs of the respective memory cell at the low voltage.

摘要翻译： 在本发明的一个实施例中，提供了可编程互连电路。 可编程互连电路包括第一和第二静态随机存取存储器单元，每个具有第一输出和第二输出。 第二个输出是第一个输出的反转。 第一和第二通过门分别耦合到相应的第一和第二存储器单元的第一和第二输出之一。 第一和第二锁定状态电路耦合到相应的第一和第二存储器单元。 响应于配置状态信号并且其中一个存储器单元的第一输出被断言为低电压，相应的锁定状态电路被配置为将各个存储单元的输出中的一个保持在低电压。

公开(公告)号：US07831873B1

公开(公告)日：2010-11-09

申请号：US11715510

申请日：2007-03-07

申请人： Stephen M. Trimberger ,  Austin H. Lesea

发明人： Stephen M. Trimberger ,  Austin H. Lesea

IPC分类号： G01R31/28 ,  G01R31/26 ,  H01L35/00 ,  H01L29/06 ,  H01J19/82 ,  G01K7/00

CPC分类号： G01K3/005 ,  G01K7/32

摘要： An integrated circuit is used to monitor and process parametric variations, such as temperature and voltage variations. An integrated circuit may include a temperature-sensitive oscillator circuit and a temperature-insensitive oscillator circuit, and frequency difference between the two sources may be monitored. In some embodiments, a parametric-insensitive reference oscillator is used as a reference to measure frequency performance of a second oscillator wherein the second oscillator performance is parametric-sensitive. The measured frequency performance is then compared to a tamper threshold and the result of the comparison is indicative of tampering.

摘要翻译： 集成电路用于监测和处理参数变化，如温度和电压变化。 集成电路可以包括温度敏感振荡器电路和不敏感温度的振荡器电路，并且可以监视两个源之间的频率差。 在一些实施例中，使用参数不敏感参考振荡器作为参考，以测量第二振荡器的频率性能，其中第二振荡器性能是参数敏感的。 然后将测量的频率性能与篡改阈值进行比较，并且比较的结果表示篡改。