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    UV-CURE PRE-TREATMENT OF CARRIER FILM FOR WAFER DICING USING HYBRID LASER SCRIBING AND PLASMA ETCH APPROACH
    24.
    发明申请
    UV-CURE PRE-TREATMENT OF CARRIER FILM FOR WAFER DICING USING HYBRID LASER SCRIBING AND PLASMA ETCH APPROACH 有权
    使用混合激光扫描和等离子体蚀刻方法进行波长涂覆的载体膜的UV固化预处理

    公开(公告)号：US20160315009A1

    公开(公告)日：2016-10-27

    申请号：US14697391

    申请日：2015-04-27

    申请人： Wei-Sheng Lei ,  Brad Eaton ,  Jungrae Park ,  Ajay Kumar ,  James S. Papanu ,  Prabhat Kumar

    发明人： Wei-Sheng Lei ,  Brad Eaton ,  Jungrae Park ,  Ajay Kumar ,  James S. Papanu ,  Prabhat Kumar

    IPC分类号： H01L21/78 ,  H01L21/683 ,  H01L21/268 ,  H01L21/67 ,  H01L21/308 ,  H01L21/3065

    CPC分类号： H01L21/78 ,  H01L21/268 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/67069 ,  H01L21/67207 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381

    摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits on a front side of the semiconductor wafer includes adhering a back side the semiconductor wafer on the dicing tape of a substrate carrier. Subsequent to adhering the semiconductor wafer on a dicing tape, the dicing tape is treated with a UV-cure process. Subsequent to treating the dicing tape with the UV-cure process, a dicing mask is formed on the front side of the semiconductor wafer, the dicing mask covering and protecting the integrated circuits. The dicing mask is patterned with a laser scribing process to provide gaps in the dicing mask, the gaps exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is plasma etched through the gaps in the dicing mask layer to singulate the integrated circuits.

    摘要翻译： 对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。 在一个示例中，在半导体晶片的正面上切割具有多个集成电路的半导体晶片的方法包括将半导体晶片的背面粘附在基板载体的切割带上。 在将半导体晶片粘附在切割带上之后，用UV固化工艺处理切割带。 在通过UV固化处理处理切割带之后，在半导体晶片的前侧形成切割掩模，该切割掩模覆盖并保护集成电路。 用激光刻划工艺对切割掩模进行图案化，以在切割掩模之间提供间隙，在半导体晶片的间隙暴露在集成电路之间。 通过切割掩模层中的间隙对半导体晶片进行等离子体蚀刻，以对集成电路进行分离。

    PROXIMITY CONTACT COVER RING FOR PLASMA DICING
    25.
    发明申请
    PROXIMITY CONTACT COVER RING FOR PLASMA DICING 审中-公开
    用于等离子体定位的接头盖

    公开(公告)号：US20160086852A1

    公开(公告)日：2016-03-24

    申请号：US14491856

    申请日：2014-09-19

    申请人： James M. Holden ,  Alexander N. Lerner ,  Ajay Kumar ,  Aparna Iyer ,  Alan Hiroshi Ouye

    发明人： James M. Holden ,  Alexander N. Lerner ,  Ajay Kumar ,  Aparna Iyer ,  Alan Hiroshi Ouye

    IPC分类号： H01L21/78 ,  H01J37/32 ,  H01L21/67 ,  H01L21/683 ,  H01L21/3065 ,  H01L21/308

    摘要： Methods of and carriers for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a cover ring for protecting a carrier and substrate assembly during an etch process includes an inner opening having a diameter smaller than the diameter of a substrate of the carrier and substrate assembly. An outer frame surrounds the inner opening. The outer frame has a bevel for accommodating an outermost portion of the substrate of the carrier and substrate assembly.

    摘要翻译： 描述了半导体晶片切割的方法和载体，每个晶片具有多个集成电路。 在一个示例中，用于在蚀刻工艺期间保护载体和基底组件的盖环包括直径小于载体和基底组件的基底的直径的内部开口。 外框围绕内开口。 外框架具有用于容纳载体和基底组件的基底的最外部分的斜面。

    DICING TAPE PROTECTION FOR WAFER DICING USING LASER SCRIBE PROCESS
    27.
    发明申请
    DICING TAPE PROTECTION FOR WAFER DICING USING LASER SCRIBE PROCESS 有权
    使用激光扫描工艺制造的波纹贴片保护

    公开(公告)号：US20150311118A1

    公开(公告)日：2015-10-29

    申请号：US14272101

    申请日：2014-05-07

    申请人： Wei-Sheng Lei ,  Brad Eaton ,  Ajay Kumar

    发明人： Wei-Sheng Lei ,  Brad Eaton ,  Ajay Kumar

    IPC分类号： H01L21/78 ,  H01L21/683

    CPC分类号： H01L21/78 ,  H01L21/67092 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L2221/68377

    摘要： Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of scribing a semiconductor wafer having a plurality of integrated circuits involves adhering a backside of a semiconductor wafer to an inner portion of a carrier tape of a substrate carrier that includes a tape frame mounted above the carrier tape. The method also involves overlaying a protective frame above a front side of the semiconductor wafer and above an exposed outer portion of the carrier tape, the protective frame having an opening exposing an inner region of the front side of the semiconductor wafer. The method also involves laser scribing the front side of the semiconductor wafer with the protective frame in place.

    摘要翻译： 对具有多个集成电路的各晶片的切割半导体晶片的方法和装置进行说明。 在一个示例中，划片具有多个集成电路的半导体晶片的方法包括将半导体晶片的背面粘附到包括安装在载带上方的带框架的基板载体的载带的内部。 该方法还包括将保护框架覆盖在半导体晶片的前侧上方并且在载带的暴露的外部部分上方，保护框架具有暴露半导体晶片的前侧的内部区域的开口。 该方法还包括用保护框架将半导体晶片的前侧激光划片就位。

    Vacuum lamination of polymeric dry films for wafer dicing using hybrid laser scribing and plasma etch approach
    28.
    发明授权
    Vacuum lamination of polymeric dry films for wafer dicing using hybrid laser scribing and plasma etch approach 有权
    使用混合激光划线和等离子体蚀刻方法对用于晶片切割的聚合物干膜进行真空层压

    公开(公告)号：US09159624B1

    公开(公告)日：2015-10-13

    申请号：US14589913

    申请日：2015-01-05

    申请人： Wei-Sheng Lei ,  Prabhat Kumar ,  James S. Papanu ,  Brad Eaton ,  Ajay Kumar

    发明人： Wei-Sheng Lei ,  Prabhat Kumar ,  James S. Papanu ,  Brad Eaton ,  Ajay Kumar

    IPC分类号： H01L21/78 ,  H01L21/8234

    CPC分类号： H01L21/78 ,  H01L21/6836 ,  H01L21/8234 ,  H01L2221/68327 ,  H01L2221/6834

    摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves laminating a polymeric mask layer onto a front side of the semiconductor wafer by dry film vacuum lamination, the polymeric mask layer covering and protecting the integrated circuits. The method also involves patterning the polymeric mask layer with a laser scribing process to provide gaps in the polymeric mask layer, the gaps exposing regions of the semiconductor wafer between the integrated circuits. The method also involves plasma etching the semiconductor wafer through the gaps in the polymeric mask layer to singulate the integrated circuits. The method also involves, subsequent to plasma etching the semiconductor wafer, removing the polymeric mask layer.

    摘要翻译： 对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。 在一个实例中，对具有多个集成电路的半导体晶片进行切割的方法包括通过干膜真空层压将聚合物掩模层层压到半导体晶片的正面上，该聚合物掩模层覆盖并保护集成电路。 该方法还包括用激光划线工艺图案化聚合物掩模层，以在聚合物掩模层中提供间隙，间隙暴露集成电路之间的半导体晶片的区域。 该方法还包括通过聚合物掩模层中的间隙等离子体蚀刻半导体晶片以对集成电路进行分离。 该方法还涉及在等离子体蚀刻半导体晶片之后，去除聚合物掩模层。

    HYBRID WAFER DICING APPROACH USING TEMPORALLY-CONTROLLED LASER SCRIBING PROCESS AND PLASMA ETCH
    29.
    发明申请
    HYBRID WAFER DICING APPROACH USING TEMPORALLY-CONTROLLED LASER SCRIBING PROCESS AND PLASMA ETCH 审中-公开
    使用温度控制激光扫描过程和等离子体蚀刻的混合波形方法

    公开(公告)号：US20150243559A1

    公开(公告)日：2015-08-27

    申请号：US14265139

    申请日：2014-04-29

    申请人： Jungrae Park ,  Wei-Sheng Lei ,  James S. Papanu ,  Brad Eaton ,  Ajay Kumar

    发明人： Jungrae Park ,  Wei-Sheng Lei ,  James S. Papanu ,  Brad Eaton ,  Ajay Kumar

    IPC分类号： H01L21/78 ,  H01L21/3065 ,  H01L21/67 ,  H01L21/308

    CPC分类号： H01L21/78 ,  B23K26/0624 ,  B23K26/0661 ,  B23K26/18 ,  B23K26/364 ,  B23K2101/40 ,  B23K2103/166 ,  B23K2103/50 ,  B23K2103/56 ,  H01L21/02057 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/32135

    摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The method also involves patterning the mask with a temporally-controlled laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The temporally-controlled laser scribing process involves scribing with a laser beam having a profile comprising a leading femto-second portion and a trailing lower-intensity, higher fluence portion. The method also involves plasma etching the semiconductor wafer through the gaps in the patterned mask to singulate the integrated circuits.

    摘要翻译： 对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。 在一个示例中，对具有多个集成电路的半导体晶片进行切割的方法包括在半导体晶片上形成掩模，该掩模包括覆盖并保护集成电路的层。 该方法还包括用时间控制的激光划线工艺对掩模进行图案化，以提供具有间隙的图案化掩模，暴露集成电路之间的半导体晶片的区域。 时间控制的激光划线方法包括用具有包括前导毫微微秒部分和尾随较低强度，较高注量部分的轮廓的激光束划线。 该方法还包括通过图案化掩模中的间隙等离子体蚀刻半导体晶片以对集成电路进行分离。