公开(公告)号：US20080151601A1

公开(公告)日：2008-06-26

申请号：US11957756

申请日：2007-12-17

申请人： Sang-beom Kang ,  Woo-yeong Cho ,  Hyung-rok Oh ,  Joon-min Park

发明人： Sang-beom Kang ,  Woo-yeong Cho ,  Hyung-rok Oh ,  Joon-min Park

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C13/0064 ,  B82Y10/00 ,  G11C11/15 ,  G11C13/0004 ,  G11C13/0014 ,  G11C13/0069 ,  G11C2013/0066 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/79

摘要： A non-volatile memory device includes a memory cell array including a memory cell array having word lines, bit lines, and non-volatile memory cells, each non-volatile memory cell having a variable resistive material and an access element connected between the corresponding word line and the corresponding bit line. The variable resistive material has a resistance level that varies according to data to be stored. A selection circuit selects at least one non-volatile memory cell in which data will be written. An adaptive write circuit/method supplies a write bias to the selected non-volatile memory cell through the bit line connected to the selected non-volatile memory cell to write data in the selected non-volatile memory cell and varies (e.g., increases) the write bias until the resistance level of the selected non-volatile memory cell varies.

摘要翻译： 非易失性存储器件包括存储单元阵列，其包括具有字线，位线和非易失性存储器单元的存储单元阵列，每个非易失性存储单元具有可变电阻材料和连接在相应字之间的存取单元 线和相应的位线。 可变电阻材料具有根据要存储的数据而变化的电阻电平。 选择电路选择要写入数据的至少一个非易失性存储单元。 自适应写入电路/方法通过连接到所选择的非易失性存储器单元的位线向所选择的非易失性存储器单元提供写入偏置，以将数据写入所选择的非易失性存储单元中并且改变（例如，增加） 写入偏置，直到所选择的非易失性存储单元的电阻水平变化。

公开(公告)号：US07352616B2

公开(公告)日：2008-04-01

申请号：US11319602

申请日：2005-12-29

申请人： Sang-beom Kang ,  Du-eung Kim ,  Hyung-rok Oh ,  Kwang-jin Lee

发明人： Sang-beom Kang ,  Du-eung Kim ,  Hyung-rok Oh ,  Kwang-jin Lee

IPC分类号： G11C11/00

CPC分类号： G11C5/145 ,  G11C8/08 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/009

摘要： A phase change random access memory on aspect includes a memory cell array block including a plurality of phase change memory cells, a column decoder, a row decoder, a column selector, and a write driver. The memory further includes a write boosting unit having a plurality of internal charge pumps which boost a first voltage to generate a write driving voltage which drives the write driver, where the number of internal charge pumps that are activated during a write operation is varied according to a number of phase change memory cells which are selected during the write operation. The memory still further includes a column boosting unit which boosts the first voltage to generate a column driving voltage which drives the column decoder, and a row boosting unit which boosts the first voltage to generate a row driving voltage which drives the row decoder.

摘要翻译： 一方面的相变随机存取存储器包括包括多个相变存储器单元，列解码器，行解码器，列选择器和写驱动器的存储单元阵列块。 存储器还包括具有多个内部电荷泵的写入升压单元，该多个内部电荷泵升压第一电压以产生驱动写入驱动器的写入驱动电压，其中在写入操作期间被激活的内部电荷泵的数量根据 在写入操作期间选择的多个相变存储器单元。 存储器还包括列升压单元，其升高第一电压以产生驱动列解码器的列驱动电压;以及行升压单元，其升高第一电压以产生驱动行解码器的行驱动电压。

公开(公告)号：US20070097741A1

公开(公告)日：2007-05-03

申请号：US11319602

申请日：2005-12-29

申请人： Sang-beom Kang ,  Du-eung Kim ,  Hyung-rok Oh ,  Kwang-jin Lee

发明人： Sang-beom Kang ,  Du-eung Kim ,  Hyung-rok Oh ,  Kwang-jin Lee

IPC分类号： G11C11/00

CPC分类号： G11C5/145 ,  G11C8/08 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/009

摘要： A phase change random access memory on aspect includes a memory cell array block including a plurality of phase change memory cells, a column decoder, a row decoder, a column selector, and a write driver. The memory further includes a write boosting unit having a plurality of internal charge pumps which boost a first voltage to generate a write driving voltage which drives the write driver, where the number of internal charge pumps that are activated during a write operation is varied according to a number of phase change memory cells which are selected during the write operation. The memory still further includes a column boosting unit which boosts the first voltage to generate a column driving voltage which drives the column decoder, and a row boosting unit which boosts the first voltage to generate a row driving voltage which drives the row decoder.

摘要翻译： 一方面的相变随机存取存储器包括包括多个相变存储器单元，列解码器，行解码器，列选择器和写驱动器的存储单元阵列块。 存储器还包括具有多个内部电荷泵的写入升压单元，该多个内部电荷泵升压第一电压以产生驱动写入驱动器的写入驱动电压，其中在写入操作期间被激活的内部电荷泵的数量根据 在写入操作期间选择的多个相变存储器单元。 存储器还包括列升压单元，其升高第一电压以产生驱动列解码器的列驱动电压;以及行升压单元，其升高第一电压以产生驱动行解码器的行驱动电压。

公开(公告)号：US07859882B2

公开(公告)日：2010-12-28

申请号：US11844511

申请日：2007-08-24

申请人： Woo-yeong Cho ,  Du-eung Kim ,  Sang-beom Kang

发明人： Woo-yeong Cho ,  Du-eung Kim ,  Sang-beom Kang

IPC分类号： G11C11/00

CPC分类号： G11C8/14 ,  G11C13/00 ,  G11C13/0023 ,  G11C13/0028 ,  G11C13/0069 ,  G11C2213/79

摘要： A resistive memory device is provided. The resistive memory device includes word lines arranged in M rows, bit lines arranged in N columns, local source lines arranged in M/2 rows, and resistive memory cells arranged in M rows and N columns. Each of the resistive memory cells includes a resistance variable element having a first electrode connected to a corresponding bit line, and a cell transistor having a first terminal connected to a second electrode of the resistance variable element, a second terminal connected to a corresponding local source line, and a control terminal connected to a corresponding word line. The local source line is commonly connected to the second terminals of the cell transistors of the two neighboring rows.

摘要翻译： 提供了一种电阻式存储器件。 电阻式存储装置包括排列成M行的字线，以N列排列的位线，以M / 2行排列的局部源极线以及布置成M行N列的电阻存储单元。 每个电阻存储单元包括电阻可变元件，电阻可变元件具有连接到对应的位线的第一电极，以及单元晶体管，其具有连接到电阻可变元件的第二电极的第一端子，连接到相应的本地源极的第二端子 线路和连接到相应字线的控制终端。 本地源极线通常连接到两个相邻行的单元晶体管的第二端子。

公开(公告)号：US08050074B2

公开(公告)日：2011-11-01

申请号：US12658807

申请日：2010-02-16

申请人： Ho-jung Kim ,  Chul-woo Park ,  Sang-beom Kang ,  Jong-wan Kim ,  Hyun-ho Choi ,  Young-pil Kim ,  Sung-chul Lee

发明人： Ho-jung Kim ,  Chul-woo Park ,  Sang-beom Kang ,  Jong-wan Kim ,  Hyun-ho Choi ,  Young-pil Kim ,  Sung-chul Lee

IPC分类号： G11C19/00

CPC分类号： G11C11/15 ,  G11C5/04

摘要： A memory device is comprised of a magnetic structure that stores information in a plurality of domains of the magnetic structure. A write unit writes information to at least one of the plurality of domains of the magnetic structure by applying a write current to the magnetic structure in response to a control signal. A read unit reads information from at least one of the plurality of domains of the magnetic structure by applying a read current to the magnetic structure in response to the control signal. A domain wall movement control unit is coupled to a portion of the magnetic structure and moves information stored in the plurality of domains in the magnetic structure to other domains in the magnetic structure in response to the control signal. The write unit, the read unit and the domain wall movement control unit are all coupled to the same control signal line that provides the control signal.

摘要翻译： 存储器件由将磁信息存储在磁结构的多个域中的磁结构构成。 写单元响应于控制信号向磁结构施加写入电流，将信息写入磁结构的多个域中的至少一个。 读取单元通过响应于控制信号向磁性结构施加读取电流，从磁性结构的多个域中的至少一个域读取信息。 畴壁移动控制单元耦合到磁结构的一部分，并且响应于控制信号将存储在磁结构中的多个域中的信息移动到磁结构中的其他区域。 写单元，读单元和域壁移动控制单元都耦合到提供控制信号的相同控制信号线。

公开(公告)号：US20050281073A1

公开(公告)日：2005-12-22

申请号：US11092456

申请日：2005-03-29

申请人： Woo-yeong Cho ,  Sang-beom Kang

发明人： Woo-yeong Cho ,  Sang-beom Kang

IPC分类号： G11C13/02 ,  G11C11/00 ,  G11C16/02

CPC分类号： G11C13/0004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/79

摘要： Programming phase-change memory devices and driver circuits for programming phase-change memory devices are provided that control an amount of current supplied to a phase-change material of the phase-change memory device based on a measure of resistance of the phase-change material during programming of the phase-change memory device. Such control may be based on detected voltage or current. The amount of current supplied to the phase-change material may be increased until the measured voltage level changes with respect to a reference voltage value and the current maintained constant if the measured voltage level has changed with respect to the reference voltage value. The change of the measured voltage level with respect to the reference voltage may be the measured voltage level falling below the reference voltage value.

摘要翻译： 提供用于编程相变存储器件的编程相变存储器件和驱动器电路，其基于相变材料的电阻的测量来控制提供给相变存储器件的相变材料的电流量 在相变存储器件的编程期间。 这种控制可以基于检测到的电压或电流。 提供给相变材料的电流量可以增加，直到测量的电压电平相对于参考电压值改变，并且如果测量的电压电平相对于参考电压值发生变化，则电流保持恒定。 相对于参考电压的测量电压电平的变化可以是测量的电压电平低于参考电压值。

公开(公告)号：US20100309705A1

公开(公告)日：2010-12-09

申请号：US12662785

申请日：2010-05-04

申请人： Seung-eon Ahn ,  Ho-jung Kim ,  Chul-woo Park ,  Sang-beom Kang ,  Hyun-ho Choi

发明人： Seung-eon Ahn ,  Ho-jung Kim ,  Chul-woo Park ,  Sang-beom Kang ,  Hyun-ho Choi

IPC分类号： G11C5/02

CPC分类号： G11C5/025 ,  G11C5/02 ,  G11C8/10 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0028 ,  G11C2213/71 ,  G11C2213/72

摘要： A stacked memory device may include a substrate, a plurality of memory groups sequentially stacked on the substrate, each memory group including at least one memory layer, a plurality of X-decoder layers, at least one of the plurality of X-decoder layers being disposed between every alternate neighboring two of the plurality of memory groups, and a plurality of Y-decoder layers disposed alternately with the plurality of X-decoder layers, at least one of the plurality of Y-decoder layers being disposed between every alternate neighboring two of the plurality of memory groups.

摘要翻译： 层叠的存储器件可以包括衬底，顺序地堆叠在衬底上的多个存储器组，每个存储器组包括至少一个存储器层，多个X译码器层，所述多个X译码器层中的至少一个是 设置在所述多个存储器组中的每个相邻的两个存储器组之间，以及与所述多个X解码器层交替布置的多个Y译码器层，所述多个Y译码器层中的至少一个设置在每个相邻的两个存储器组之间 的多个存储器组。

公开(公告)号：US07586775B2

公开(公告)日：2009-09-08

申请号：US11850130

申请日：2007-09-05

申请人： Sang-beom Kang ,  Yong-jin Yoon ,  Qi Wang

发明人： Sang-beom Kang ,  Yong-jin Yoon ,  Qi Wang

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/009

摘要： A nonvolatile memory device comprises a first voltage generation unit, a second voltage generation unit, a first circuit block, and a discharge unit. The first voltage generation unit generates a first voltage with a first magnitude. The second voltage generation unit generates a second voltage with a second magnitude greater than the first magnitude. The first circuit block selectively receives the first voltage or the second voltage through an input node. The discharge unit discharges the input node between a time point where the input node has been charged with the second voltage and a time point where the input node receives the first voltage.

摘要翻译： 非易失性存储器件包括第一电压产生单元，第二电压产生单元，第一电路块和放电单元。 第一电压产生单元产生具有第一量值的第一电压。 第二电压产生单元产生具有大于第一幅值的第二幅度的第二电压。 第一电路块通过输入节点选择性地接收第一电压或第二电压。 放电单元在输入节点已经被充电的时间点与第二电压之间和输入节点接收到第一电压的时间点之间对输入节点进行放电。

公开(公告)号：US07190607B2

公开(公告)日：2007-03-13

申请号：US11092456

申请日：2005-03-29

申请人： Woo-yeong Cho ,  Sang-beom Kang

发明人： Woo-yeong Cho ,  Sang-beom Kang

IPC分类号： G11C11/00

CPC分类号： G11C13/0004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/79

摘要： Programming phase-change memory devices and driver circuits for programming phase-change memory devices are provided that control an amount of current supplied to a phase-change material of the phase-change memory device based on a measure of resistance of the phase-change material during programming of the phase-change memory device. Such control may be based on detected voltage or current. The amount of current supplied to the phase-change material may be increased until the measured voltage level changes with respect to a reference voltage value and the current maintained constant if the measured voltage level has changed with respect to the reference voltage value. The change of the measured voltage level with respect to the reference voltage may be the measured voltage level falling below the reference voltage value.

摘要翻译： 提供用于编程相变存储器件的编程相变存储器件和驱动器电路，其基于相变材料的电阻的测量来控制提供给相变存储器件的相变材料的电流量 在相变存储器件的编程期间。 这种控制可以基于检测到的电压或电流。 提供给相变材料的电流量可以增加，直到测量的电压电平相对于参考电压值改变，并且如果测量的电压电平相对于参考电压值发生变化，则电流保持恒定。 相对于参考电压的测量电压电平的变化可以是测量的电压电平低于参考电压值。

公开(公告)号：US20060221679A1

公开(公告)日：2006-10-05

申请号：US11315129

申请日：2005-12-23

申请人： Sang-beom Kang ,  Du-eung Kim ,  Baek-hyung Cho ,  Hye-jin Kim

发明人： Sang-beom Kang ,  Du-eung Kim ,  Baek-hyung Cho ,  Hye-jin Kim

IPC分类号： G11C11/00

CPC分类号： G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/79

摘要： A method of programming a memory array including a plurality of memory cells is provided. The memory cells may include phase-change memory elements. In one aspect, the method includes applying in succession first through nth current pulses to each of the memory cells to be programmed to a first state (e.g., a crystalline state), where a current amplitude of the first through nth current pulses decreases with each successive pulse, and where a pulse duration of the first through nth current pulses increases with each successive pulse.

摘要翻译： 提供了一种编程包括多个存储单元的存储器阵列的方法。 存储器单元可以包括相变存储元件。 在一个方面，所述方法包括首先连续地将每个存储单元连续施加到要编程到第一状态（例如，结晶状态）的第n个/ 第一至第n个电流脉冲随着每个连续脉冲而减小，并且其中第一至第n个电流脉冲的脉冲持续时间随每个连续脉冲而增加。