利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

23 条记录 (耗时 0.065 秒)

    Magnetic packet memory storage devices, memory systems including such devices, and methods of controlling such devices
    1.
    发明申请
    Magnetic packet memory storage devices, memory systems including such devices, and methods of controlling such devices 失效
    磁性分组存储器存储设备，包括这种设备的存储器系统以及控制这些设备的方法

    公开(公告)号：US20100208381A1

    公开(公告)日：2010-08-19

    申请号：US12658807

    申请日：2010-02-16

    申请人： Ho-jung Kim ,  Chul-woo Park ,  Sang-beom Kang ,  Jong-wan Kim ,  Hyun-ho Choi ,  Young-pil Kim ,  Sung-chul Lee

    发明人： Ho-jung Kim ,  Chul-woo Park ,  Sang-beom Kang ,  Jong-wan Kim ,  Hyun-ho Choi ,  Young-pil Kim ,  Sung-chul Lee

    IPC分类号： G11B19/02

    CPC分类号： G11C11/15 ,  G11C5/04

    摘要： A memory device is comprised of a magnetic structure that stores information in a plurality of domains of the magnetic structure. A write unit writes information to at least one of the plurality of domains of the magnetic structure by applying a write current to the magnetic structure in response to a control signal. A read unit reads information from at least one of the plurality of domains of the magnetic structure by applying a read current to the magnetic structure in response to the control signal. A domain wall movement control unit is coupled to a portion of the magnetic structure and moves information stored in the plurality of domains in the magnetic structure to other domains in the magnetic structure in response to the control signal. The write unit, the read unit and the domain wall movement control unit are all coupled to the same control signal line that provides the control signal.

    摘要翻译： 存储器件由将磁信息存储在磁结构的多个域中的磁结构构成。 写单元响应于控制信号向磁结构施加写入电流，将信息写入磁结构的多个域中的至少一个。 读取单元通过响应于控制信号向磁性结构施加读取电流，从磁性结构的多个域中的至少一个域读取信息。 畴壁移动控制单元耦合到磁结构的一部分，并且响应于控制信号将存储在磁结构中的多个域中的信息移动到磁结构中的其他区域。 写单元，读单元和域壁移动控制单元都耦合到提供控制信号的相同控制信号线。

    Magnetic packet memory storage devices, memory systems including such devices, and methods of controlling such devices
    2.
    发明授权
    Magnetic packet memory storage devices, memory systems including such devices, and methods of controlling such devices 失效
    磁性分组存储器存储设备，包括这种设备的存储器系统以及控制这些设备的方法

    公开(公告)号：US08050074B2

    公开(公告)日：2011-11-01

    申请号：US12658807

    申请日：2010-02-16

    申请人： Ho-jung Kim ,  Chul-woo Park ,  Sang-beom Kang ,  Jong-wan Kim ,  Hyun-ho Choi ,  Young-pil Kim ,  Sung-chul Lee

    发明人： Ho-jung Kim ,  Chul-woo Park ,  Sang-beom Kang ,  Jong-wan Kim ,  Hyun-ho Choi ,  Young-pil Kim ,  Sung-chul Lee

    IPC分类号： G11C19/00

    CPC分类号： G11C11/15 ,  G11C5/04

    摘要： A memory device is comprised of a magnetic structure that stores information in a plurality of domains of the magnetic structure. A write unit writes information to at least one of the plurality of domains of the magnetic structure by applying a write current to the magnetic structure in response to a control signal. A read unit reads information from at least one of the plurality of domains of the magnetic structure by applying a read current to the magnetic structure in response to the control signal. A domain wall movement control unit is coupled to a portion of the magnetic structure and moves information stored in the plurality of domains in the magnetic structure to other domains in the magnetic structure in response to the control signal. The write unit, the read unit and the domain wall movement control unit are all coupled to the same control signal line that provides the control signal.

    摘要翻译： 存储器件由将磁信息存储在磁结构的多个域中的磁结构构成。 写单元响应于控制信号向磁结构施加写入电流，将信息写入磁结构的多个域中的至少一个。 读取单元通过响应于控制信号向磁性结构施加读取电流，从磁性结构的多个域中的至少一个域读取信息。 畴壁移动控制单元耦合到磁结构的一部分，并且响应于控制信号将存储在磁结构中的多个域中的信息移动到磁结构中的其他区域。 写单元，读单元和域壁移动控制单元都耦合到提供控制信号的相同控制信号线。

    Phase-change and resistance-change random access memory devices and related methods of performing burst mode operations in such memory devices
    5.
    发明授权
    Phase-change and resistance-change random access memory devices and related methods of performing burst mode operations in such memory devices 有权
    相变和电阻变化随机存取存储器件以及在这种存储器件中执行突发模式操作的相关方法

    公开(公告)号：US08218360B2

    公开(公告)日：2012-07-10

    申请号：US12582880

    申请日：2009-10-21

    申请人： Kwang-Jin Lee ,  Young-kug Moon ,  Young-pil Kim

    发明人： Kwang-Jin Lee ,  Young-kug Moon ,  Young-pil Kim

    IPC分类号： G11C11/00 ,  G11C7/00

    CPC分类号： G11C13/004 ,  G11C7/1018 ,  G11C8/18 ,  G11C11/5678 ,  G11C13/00 ,  G11C13/0004

    摘要： Phase-change and resistance-change random access memory devices are provided which include a phase-change or resistance-change memory cell array and a sense amplifier that is configured to amplify data read from the phase-change memory cell array. These random access memory devices are configured to read data from a first word line of the phase-change or resistance-change memory cell array and to insert a dummy burst in which no data is read when a first boundary crossing occurs during a burst mode operation. Related methods of operating phase-change and/or resistance-change random access memory devices in burst mode are also provided.

    摘要翻译： 提供了相变和电阻变化随机存取存储器件，其包括相变或电阻变化存储单元阵列和被配置为放大从相变存储单元阵列读取的数据的读出放大器。 这些随机存取存储器件被配置为从相变或电阻变化存储单元阵列的第一字线读取数据，并且在突发模式操作期间发生第一边界交叉时插入其中没有读取数据的虚拟脉冲串 。 还提供了以突发模式操作相变和/或电阻变化随机存取存储器件的相关方法。

    Phase-Change and Resistance-Change Random Access Memory Devices and Related Methods of Performing Burst Mode Operations in Such Memory Devices
    6.
    发明申请
    Phase-Change and Resistance-Change Random Access Memory Devices and Related Methods of Performing Burst Mode Operations in Such Memory Devices 有权
    相变和电阻变化随机存取存储器件以及在这种存储器件中执行突发模式操作的相关方法

    公开(公告)号：US20100124102A1

    公开(公告)日：2010-05-20

    申请号：US12582880

    申请日：2009-10-21

    申请人： Kwang-Jin Lee ,  Young-kug Moon ,  Young-pil Kim

    发明人： Kwang-Jin Lee ,  Young-kug Moon ,  Young-pil Kim

    IPC分类号： G11C11/00 ,  G11C7/00

    CPC分类号： G11C13/004 ,  G11C7/1018 ,  G11C8/18 ,  G11C11/5678 ,  G11C13/00 ,  G11C13/0004

    摘要： Phase-change and resistance-change random access memory devices are provided which include a phase-change or resistance-change memory cell array and a sense amplifier that is configured to amplify data read from the phase-change memory cell array. These random access memory devices are configured to read data from a first word line of the phase-change or resistance-change memory cell array and to insert a dummy burst in which no data is read when a first boundary crossing occurs during a burst mode operation. Related methods of operating phase-change and/or resistance-change random access memory devices in burst mode are also provided.

    摘要翻译： 提供了相变和电阻变化随机存取存储器件，其包括相变或电阻变化存储单元阵列和被配置为放大从相变存储单元阵列读取的数据的读出放大器。 这些随机存取存储器件被配置为从相变或电阻变化存储单元阵列的第一字线读取数据，并且在突发模式操作期间发生第一边界交叉时插入其中没有读取数据的虚拟脉冲串 。 还提供了以突发模式操作相变和/或电阻变化随机存取存储器件的相关方法。

    Semiconductor device test patterns and related methods for precisely measuring leakage currents in semiconductor cell transistors
    7.
    发明授权
    Semiconductor device test patterns and related methods for precisely measuring leakage currents in semiconductor cell transistors 失效
    用于精确测量半导体单元晶体管中的漏电流的半导体器件测试图案和相关方法

    公开(公告)号：US07271408B2

    公开(公告)日：2007-09-18

    申请号：US10796672

    申请日：2004-03-09

    申请人： Young-pil Kim ,  Beom-jun Jin

    发明人： Young-pil Kim ,  Beom-jun Jin

    IPC分类号： H01L23/58

    CPC分类号： H01L27/10882 ,  H01L22/32 ,  H01L27/108 ,  H01L27/10814 ,  H01L27/10894 ,  H01L27/10897 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Semiconductor device test patterns are provided that include a word line on a semiconductor substrate and an active region having a first impurity doped region and a second impurity doped region in at the semiconductor substrate. A first self-aligned contact pad is electrically connected to the first impurity doped region, and a first direct contact is electrically connected to the first self-aligned contact pad. A first bit line is electrically connected to the first direct contact, and a first probing pad is electrically connected to the first bit line. The test pattern further includes a second self-aligned contact pad that is electrically connected to the second impurity doped region, and a second direct contact electrically connected to the second self-aligned contact pad. A second conductive line is electrically connected to the second direct contact, and a second probing pad is electrically connected to the second conductive line. These test patterns may be used to measure leakage current in a cell transistor of the semiconductor device.

    摘要翻译： 提供半导体器件测试图案，其包括在半导体衬底上的字线和在半导体衬底中具有第一杂质掺杂区和第二杂质掺杂区的有源区。 第一自对准接触焊盘电连接到第一杂质掺杂区域，第一直接接触电连接到第一自对准接触焊盘。 第一位线电连接到第一直接触点，并且第一探针焊盘电连接到第一位线。 测试图案还包括电连接到第二杂质掺杂区的第二自对准接触焊盘和电连接到第二自对准接触焊盘的第二直接接触。 第二导电线电连接到第二直接接触，第二探测焊盘电连接到第二导线。 这些测试图案可用于测量半导体器件的单元晶体管中的漏电流。

    Write driver circuit for phase-change memory, memory including the same, and associated methods
    8.
    发明授权
    Write driver circuit for phase-change memory, memory including the same, and associated methods 有权
    为相变存储器写入驱动电路，包含相同的存储器及相关方法

    公开(公告)号：US07864619B2

    公开(公告)日：2011-01-04

    申请号：US12292200

    申请日：2008-11-13

    申请人： Beak-hyung Cho ,  Kwang-ho Kim ,  Young-pil Kim

    发明人： Beak-hyung Cho ,  Kwang-ho Kim ,  Young-pil Kim

    IPC分类号： G11C8/00 ,  G11C5/14 ,  G11C11/00

    CPC分类号： G11C13/0038 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/0069 ,  G11C2013/0078

    摘要： A write driver circuit for a memory that includes phase-change memory cells changeable between a RESET state resistance and a SET state resistance in response to an applied current pulse, the write driver circuit including a write current level adjusting unit configured to determine first to n-th SET state current levels in response to a SET state current level signal, where n is an integer greater than 1, and configured to determine a RESET state current level in response to a RESET state current level signal, and a write current output unit configured to generate one of a SET state current pulse and a RESET state current pulse corresponding to a SET state current level or a RESET state current level determined by the write current level adjusting unit.

    摘要翻译： 一种用于存储器的写入驱动器电路，其包括响应于所施加的电流脉冲而在RESET状态电阻和SET状态电阻之间改变的相变存储器单元，所述写入驱动器电路包括写入电平电平调整单元，其被配置为从第一至第n 响应于SET状态电流电平信号，其中n是大于1的整数，并且被配置为响应于RESET状态电流信号确定RESET状态电流电平，并且写入电流输出单元 被配置为产生与由写入电平电平调整单元确定的SET状态电流电平或RESET状态电流电平对应的SET状态电流脉冲和RESET状态电流脉冲之一。

    Methods of forming integrated circuits having memory cell arrays and peripheral circuits therein
    10.
    发明授权
    Methods of forming integrated circuits having memory cell arrays and peripheral circuits therein 失效
    在其中形成具有存储单元阵列和外围电路的集成电路的方法

    公开(公告)号：US5981324A

    公开(公告)日：1999-11-09

    申请号：US956584

    申请日：1997-10-23

    申请人： Young-woo Seo ,  Young-pil Kim ,  Myeon-koo Kang ,  Won-shik Lee

    发明人： Young-woo Seo ,  Young-pil Kim ,  Myeon-koo Kang ,  Won-shik Lee

    IPC分类号： H01L21/8239 ,  H01L21/8242

    CPC分类号： H01L27/10844 ,  H01L27/1052

    摘要： Methods of forming integrated circuits having memory cell arrays therein and peripheral circuits therein include the steps of selectively forming more lightly doped source and drain regions for transistors in the memory cell arrays. These more lightly doped source and drain regions are designed to have fewer crystalline defects therein caused by ion implantation, so that storage capacitors coupled thereto have improved refresh characteristics. Preferred methods include the steps of forming a first well region of first conductivity type (e.g., P-type) in a memory cell portion of a semiconductor substrate and a second well region of first conductivity type in a peripheral circuit portion of the semiconductor substrate extending adjacent the memory cell portion. First and second insulated gate electrodes are then formed on the first and second well regions, respectively, using conventional techniques. First dopants of second conductivity type are then implanted at a first dose level into the first and second well regions, using the first and second insulated gate electrodes as an implant mask. These dopants are then diffused to form lightly doped source and drain regions adjacent the first and second insulated gate electrodes. Second dopants of second conductivity type are then selectively implanted at a second dose level, greater than the first dose level, into the second well region using self-alignment techniques. However, these dopants are preferably not implanted into the first well region. These second dopants are then diffused into the second source/drain regions.

    摘要翻译： 形成其中具有存储单元阵列的集成电路及其外围电路的方法包括以下步骤：为存储单元阵列中的晶体管选择性地形成更多的轻掺杂源极和漏极区域。 这些更轻掺杂的源极和漏极区域被设计为在离子注入中具有较少的晶体缺陷，使得与其耦合的存储电容器具有改善的刷新特性。 优选的方法包括以下步骤：在半导体衬底的存储单元部分中形成第一导电类型的第一阱区域（例如，P型）和在半导体衬底延伸的外围电路部分中的第一导电类型的第二阱区域 邻近存储单元部分。 然后使用常规技术分别在第一和第二阱区上形成第一和第二绝缘栅电极。 然后使用第一和第二绝缘栅电极作为植入掩模，将第一导电类型的第一掺杂剂以第一剂量水平注入第一阱区和第二阱区。 然后这些掺杂剂被扩散以形成与第一和第二绝缘栅电极相邻的轻掺杂源极和漏极区。 然后使用自对准技术将第二导电类型的第二掺杂剂以大于第一剂量水平的第二剂量水平选择性地植入第二阱区。 然而，这些掺杂剂优选不被植入第一阱区。 然后将这些第二掺杂剂扩散到第二源/漏区。