Nonvolatile memory device having memory and reference cells
    1.
    发明授权
    Nonvolatile memory device having memory and reference cells 有权
    具有存储器和参考单元的非易失性存储器件

    公开(公告)号:US07843716B2

    公开(公告)日:2010-11-30

    申请号:US12031085

    申请日:2008-02-14

    IPC分类号: G11C5/02

    摘要: A nonvolatile memory device includes a stack-type memory cell array, a selection circuit and a read circuit. The memory cell array includes multiple memory cell layers and a reference cell layer, which are vertically laminated. Each of the memory cell layers includes multiple nonvolatile memory cells for storing data, and the reference cell layer includes multiple reference cells for storing reference data. The selection circuit selects a nonvolatile memory cell from the memory cell layers and at least one reference cell, corresponding to the selected nonvolatile memory cell, from the reference cell layer. The read circuit supplies a read bias to the selected nonvolatile memory cell and the selected reference cell corresponding to the selected nonvolatile memory cell, and reads data from the selected nonvolatile memory cell.

    摘要翻译: 非易失性存储器件包括堆叠型存储单元阵列,选择电路和读取电路。 存储单元阵列包括垂直层叠的多个存储单元层和参考单元层。 每个存储单元层包括用于存储数据的多个非易失性存储单元,参考单元层包括用于存储参考数据的多个参考单元。 选择电路从参考单元层从存储单元层和对应于所选择的非易失性存储单元的至少一个参考单元选择非易失性存储单元。 读取电路向所选择的非易失性存储单元和与所选择的非易失性存储单元相对应的所选择的参考单元提供读偏置,并从所选择的非易失性存储单元读取数据。

    Multi-layer semiconductor memory device comprising error checking and correction (ECC) engine and related ECC method
    2.
    发明授权
    Multi-layer semiconductor memory device comprising error checking and correction (ECC) engine and related ECC method 有权
    多层半导体存储器件包括纠错(ECC)引擎和相关的ECC方法

    公开(公告)号:US08136017B2

    公开(公告)日:2012-03-13

    申请号:US12036414

    申请日:2008-02-25

    IPC分类号: G11C29/00

    CPC分类号: G06F11/1008 G11C5/02

    摘要: Embodiments of the invention provide a multi-layer semiconductor memory device and a related error checking and correction (ECC) method. The multi-layer semiconductor memory device includes first and second memory cell array layers, wherein the first memory cell array layer stores first payload data. The multi-layer semiconductor memory device also includes an ECC engine selectively connected to the second memory cell array layer and configured to receive the first payload data, generate first parity data corresponding to the first payload data, and store the first parity data exclusively in the second memory cell array layer.

    摘要翻译: 本发明的实施例提供一种多层半导体存储器件和相关的错误校正和校正(ECC)方法。 多层半导体存储器件包括第一和第二存储单元阵列层,其中第一存储单元阵列层存储第一有效载荷数据。 多层半导体存储器件还包括选择性地连接到第二存储单元阵列层并被配置为接收第一有效载荷数据的ECC引擎,生成与第一有效载荷数据相对应的第一奇偶校验数据,并将第一奇偶校验数据专门存储在 第二存储单元阵列层。

    Circuits and methods for adaptive write bias driving of resistive non-volatile memory devices
    3.
    发明授权
    Circuits and methods for adaptive write bias driving of resistive non-volatile memory devices 失效
    电阻性非易失性存储器件的自适应写入偏置驱动的电路和方法

    公开(公告)号:US07920405B2

    公开(公告)日:2011-04-05

    申请号:US11957756

    申请日:2007-12-17

    IPC分类号: G11C11/00 G11C11/36

    摘要: A non-volatile memory device includes a memory cell array including a memory cell array having word lines, bit lines, and non-volatile memory cells, each non-volatile memory cell having a variable resistive material and an access element connected between the corresponding word line and the corresponding bit line. The variable resistive material has a resistance level that varies according to data to be stored. A selection circuit selects at least one non-volatile memory cell in which data will be written. An adaptive write circuit/method supplies a write bias to the selected non-volatile memory cell through the bit line connected to the selected non-volatile memory cell to write data in the selected non-volatile memory cell and varies (e.g., increases) the write bias until the resistance level of the selected non-volatile memory cell varies.

    摘要翻译: 非易失性存储器件包括存储单元阵列,其包括具有字线,位线和非易失性存储器单元的存储单元阵列,每个非易失性存储单元具有可变电阻材料和连接在相应字之间的存取元件 线和相应的位线。 可变电阻材料具有根据要存储的数据而变化的电阻电平。 选择电路选择要写入数据的至少一个非易失性存储单元。 自适应写入电路/方法通过连接到所选择的非易失性存储器单元的位线向所选择的非易失性存储器单元提供写入偏置,以将数据写入所选择的非易失性存储单元中并且改变(例如,增加) 写入偏置,直到所选择的非易失性存储单元的电阻水平变化。

    Bi-directional resistive random access memory capable of multi-decoding and method of writing data thereto
    4.
    发明授权
    Bi-directional resistive random access memory capable of multi-decoding and method of writing data thereto 有权
    能够进行多重解码的双向电阻随机存取存储器及其数据写入方法

    公开(公告)号:US07869256B2

    公开(公告)日:2011-01-11

    申请号:US11957812

    申请日:2007-12-17

    IPC分类号: G11C11/00 G11C11/14

    摘要: A non-volatile memory device is employed in which data values are determined by the polarities at both ends of a cell, The non-volatile memory device includes a first decoder which decodes a plurality of predetermined bit values of a row address into a first address and is disposed in a row direction of a memory cell array; a second decoder which decodes the other bit values of the row address into a second address and is disposed in a column direction of the memory cell array; and a driver which applies bias voltages to a word line which corresponds to the first address or the second address in accordance with the data values. By including first and second decoders and decoding a row address in two steps, a bi-directional RRAM according to the present invention can perform addressing at high speeds while reducing chip size.

    摘要翻译: 使用非易失性存储器件,其中数据值由单元两端的极性确定。非易失性存储器件包括将行地址的多个预定位值解码为第一地址的第一解码器 并且设置在存储单元阵列的行方向上; 第二解码器,其将所述行地址的其他位值解码为第二地址,并且被布置在所述存储单元阵列的列方向上; 以及根据数据值对与第一地址或第二地址对应的字线施加偏置电压的驱动器。 通过包括第一和第二解码器并以两个步骤对行地址进行解码,根据本发明的双向RRAM可以在降低芯片尺寸的同时以高速执行寻址。

    Nonvolatile memory device using resistance material
    5.
    发明授权
    Nonvolatile memory device using resistance material 有权
    使用电阻材料的非易失性存储器件

    公开(公告)号:US07924639B2

    公开(公告)日:2011-04-12

    申请号:US12031115

    申请日:2008-02-14

    IPC分类号: G11C7/00 G11C29/00

    摘要: The present invention provides a nonvolatile memory device that uses a resistance material. The nonvolatile memory device includes: a stacked memory cell array having a plurality of memory cell layers stacked in a vertical direction, the stacked memory cell array having at least one memory cell group and at least one redundancy memory cell group; and a repair control circuit coupled to the stacked memory cell array, the repair control circuit configured to repair a defective one of the at least one memory cell group with a selected one of the at least one redundancy memory cell group. The features that enable repair improve the fabrication yield of the nonvolatile memory device.

    摘要翻译: 本发明提供一种使用电阻材料的非易失性存储器件。 非易失性存储器件包括:堆叠存储单元阵列,具有沿垂直方向堆叠的多个存储单元层,所述堆叠存储单元阵列具有至少一个存储单元组和至少一个冗余存储单元组; 以及修复控制电路,其耦合到所述堆叠的存储单元阵列,所述修复控制电路被配置为用所述至少一个冗余存储器单元组中的所选择的一个来修复所述至少一个存储单元组中的有缺陷的一个。 能够修复的特征提高了非易失性存储器件的制造成品率。

    Methods of Driving Nonvolatile Memory Devices that Utilize Read/Write Merge Circuits
    6.
    发明申请
    Methods of Driving Nonvolatile Memory Devices that Utilize Read/Write Merge Circuits 审中-公开
    驱动使用读/写合并电路的非易失性存储器件的方法

    公开(公告)号:US20110170332A1

    公开(公告)日:2011-07-14

    申请号:US13011188

    申请日:2011-01-21

    IPC分类号: G11C11/00 G11C7/00

    摘要: An integrated circuit memory device includes an array of nonvolatile memory cells (e.g., variable resistance cells) having a first plurality of lines electrically coupled to memory cells therein. A read/write control circuit is provided. The read/write control circuit includes a read/write merge circuit and a column selection circuit. The read/write control circuit, which is configured to drive a selected one of the first plurality of lines with unequal write and read voltages during respective write and read operations, includes a compensating unit. This compensating unit is configured to provide a read compensation current to the selected one of the first plurality of lines circuit during the read operation.

    摘要翻译: 集成电路存储器件包括具有电耦合到其中的存储器单元的第一多个线的非易失性存储器单元阵列(例如,可变电阻单元)。 提供读/写控制电路。 读/写控制电路包括读/写合并电路和列选择电路。 被配置为在相应的写入和读取操作期间以不相等的写入和读取电压驱动所述第一多个线路中的所选择的一个线路的所述读取/写入控制电路包括补偿单元。 该补偿单元被配置为在读取操作期间向第一多个线路电路中的所选择的一个电路提供读取补偿电流。

    Nonvolatile memory devices that utilize read/write merge circuits
    7.
    发明授权
    Nonvolatile memory devices that utilize read/write merge circuits 失效
    使用读/写合并电路的非易失性存储器件

    公开(公告)号:US07894236B2

    公开(公告)日:2011-02-22

    申请号:US11945443

    申请日:2007-11-27

    IPC分类号: G11C7/00 G11C7/12

    摘要: An integrated circuit memory device includes an array of nonvolatile memory cells (e.g., variable resistance cells) having a first plurality of lines electrically coupled to memory cells therein. A read/write control circuit is provided. The read/write control circuit includes a read/write merge circuit and a column selection circuit. The read/write control circuit, which is configured to drive a selected one of the first plurality of lines with unequal write and read voltages during respective write and read operations, includes a compensating unit. This compensating unit is configured to provide a read compensation current to the selected one of the first plurality of lines circuit during the read operation.

    摘要翻译: 集成电路存储器件包括具有电耦合到其中的存储器单元的第一多个线的非易失性存储器单元阵列(例如,可变电阻单元)。 提供读/写控制电路。 读/写控制电路包括读/写合并电路和列选择电路。 被配置为在相应的写入和读取操作期间以不相等的写入和读取电压驱动所述第一多个线路中的所选择的一个线路的所述读取/写入控制电路包括补偿单元。 该补偿单元被配置为在读取操作期间向第一多个线路电路中的所选择的一个电路提供读取补偿电流。

    Non-volatile memory including sub cell array and method of writing data thereto
    8.
    发明授权
    Non-volatile memory including sub cell array and method of writing data thereto 有权
    包括子单元阵列的非易失性存储器和向其写入数据的方法

    公开(公告)号:US07701747B2

    公开(公告)日:2010-04-20

    申请号:US11958432

    申请日:2007-12-18

    IPC分类号: G11C7/00

    摘要: A non-volatile memory device, in which data values are determined by polarities at cell terminals, includes a memory cell array. The memory cell array is divided into multiple sub cell arrays, each sub cell array including at least one input/output line and an X-decoder/driver. First input/output lines included in different sub cell arrays may be simultaneously activated and bias voltages may be applied to the activated first input/output lines in accordance with the data values. The non-volatile memory device may be a bi-directional resistive random access memory (RRAM).

    摘要翻译: 其中数据值由单元终端的极性确定的非易失性存储器件包括存储单元阵列。 存储单元阵列被分成多个子单元阵列,每个子单元阵列包括至少一个输入/输出线和X解码器/驱动器。 可以同时激活包括在不同子单元阵列中的第一输入/输出线,并且可以根据数据值将偏置电压施加到激活的第一输入/输出线。 非易失性存储器件可以是双向电阻随机存取存储器(RRAM)。

    Nonvolatile Memory Devices that Utilize Read/Write Merge Circuits
    9.
    发明申请
    Nonvolatile Memory Devices that Utilize Read/Write Merge Circuits 失效
    使用读/写合并电路的非易失性存储器件

    公开(公告)号:US20080151652A1

    公开(公告)日:2008-06-26

    申请号:US11945443

    申请日:2007-11-27

    IPC分类号: G11C7/00

    摘要: An integrated circuit memory device includes an array of nonvolatile memory cells (e.g., variable resistance cells) having a first plurality of lines electrically coupled to memory cells therein. A read/write control circuit is provided. The read/write control circuit includes a read/write merge circuit and a column selection circuit. The read/write control circuit, which is configured to drive a selected one of the first plurality of lines with unequal write and read voltages during respective write and read operations, includes a compensating unit. This compensating unit is configured to provide a read compensation current to the selected one of the first plurality of lines circuit during the read operation.

    摘要翻译: 集成电路存储器件包括具有电耦合到其中的存储器单元的第一多个线的非易失性存储器单元阵列(例如,可变电阻单元)。 提供读/写控制电路。 读/写控制电路包括读/写合并电路和列选择电路。 被配置为在相应的写入和读取操作期间以不相等的写入和读取电压驱动所述第一多个线路中的所选择的一个线路的所述读取/写入控制电路包括补偿单元。 该补偿单元被配置为在读取操作期间向第一多个线路电路中的所选择的一个电路提供读取补偿电流。

    CIRCUITS AND METHODS FOR ADAPTIVE WRITE BIAS DRIVING OF RESISTIVE NON-VOLATILE MEMORY DEVICES
    10.
    发明申请
    CIRCUITS AND METHODS FOR ADAPTIVE WRITE BIAS DRIVING OF RESISTIVE NON-VOLATILE MEMORY DEVICES 失效
    电阻非易失性存储器件自适应写入驱动的电路和方法

    公开(公告)号:US20080151601A1

    公开(公告)日:2008-06-26

    申请号:US11957756

    申请日:2007-12-17

    IPC分类号: G11C11/00 G11C7/00

    摘要: A non-volatile memory device includes a memory cell array including a memory cell array having word lines, bit lines, and non-volatile memory cells, each non-volatile memory cell having a variable resistive material and an access element connected between the corresponding word line and the corresponding bit line. The variable resistive material has a resistance level that varies according to data to be stored. A selection circuit selects at least one non-volatile memory cell in which data will be written. An adaptive write circuit/method supplies a write bias to the selected non-volatile memory cell through the bit line connected to the selected non-volatile memory cell to write data in the selected non-volatile memory cell and varies (e.g., increases) the write bias until the resistance level of the selected non-volatile memory cell varies.

    摘要翻译: 非易失性存储器件包括存储单元阵列,其包括具有字线,位线和非易失性存储器单元的存储单元阵列,每个非易失性存储单元具有可变电阻材料和连接在相应字之间的存取单元 线和相应的位线。 可变电阻材料具有根据要存储的数据而变化的电阻电平。 选择电路选择要写入数据的至少一个非易失性存储单元。 自适应写入电路/方法通过连接到所选择的非易失性存储器单元的位线向所选择的非易失性存储器单元提供写入偏置,以将数据写入所选择的非易失性存储单元中并且改变(例如,增加) 写入偏置,直到所选择的非易失性存储单元的电阻水平变化。