公开(公告)号：US06982954B2

公开(公告)日：2006-01-03

申请号：US09848175

申请日：2001-05-03

申请人： Sang Hoo Dhong ,  Harm Peter Hofstee

发明人： Sang Hoo Dhong ,  Harm Peter Hofstee

IPC分类号： G01R31/08

CPC分类号： G06F11/2007

摘要： A communications bus (300) includes a number of alternate transmission paths (311, 312) between a given source node (301) and respective destination node (305) on a common substrate. The source node (301) receives a signal from a first circuit (309) serviced by the bus (300) while the respective destination node (305) transfers that signal to a second circuit (310) serviced by the bus. The communications bus (300) includes two switching arrangements for switching between the alternate transmission paths (311, 312). A source switching arrangement (318) is interposed between the source node (301) and the respective alternate transmission path (311, 312). This source switching arrangement (318) selectively connects the respective source node (301) to a selected one of the alternate transmission paths (311, 312) and disconnects the source node (301) from each other alternate transmission path. A destination switching arrangement (319) is interposed between the destination node (305) and respective alternate transmission paths (311, 312). The destination switching arrangement (319) selectively connects the respective destination node (305) to the selected alternate transmission path and disconnects the respective destination node from each other alternate transmission path.

摘要翻译： 通信总线（300）包括在公共基板上的给定源节点（301）和相应目的地节点（305）之间的多个替代传输路径（311,312）。 源节点（301）从由总线（300）服务的第一电路（309）接收信号，而各个目的地节点（305）将该信号传送到由总线服务的第二电路（310）。 通信总线（300）包括用于在备选传输路径（311,312）之间切换的两个切换装置。 源切换装置（318）插入在源节点（301）和相应的备选传输路径（311,312）之间。 该源切换装置（318）选择性地将相应的源节点（301）连接到所选择的一个备选传输路径（311,312），并且将源节点（301）与彼此的替代传输路径断开连接。 目的地交换装置（319）介于目的地节点（305）和相应的备选传输路径（311,312）之间。 目的地交换装置（319）选择性地将各目的地节点（305）连接到所选择的备选传输路径，并且将相应的目的地节点与彼此的备选传输路径断开连接。

公开(公告)号：US06915506B2

公开(公告)日：2005-07-05

申请号：US09817138

申请日：2001-03-27

申请人： Sang Hoo Dhong ,  Sam Dinkin ,  Harm Peter Hofstee ,  Stephen Douglas Posluszny

发明人： Sang Hoo Dhong ,  Sam Dinkin ,  Harm Peter Hofstee ,  Stephen Douglas Posluszny

IPC分类号： G06F17/50 ,  G06F9/44

CPC分类号： G06F17/50

摘要： A method and structure for optimizing a solution for a complex problem typically solved by software tools includes selectively converting problem data into a format appropriate for one or more preselected vendor's set of solution tools and inputting the formatted design data into the one or more preselected vendor's set of solution tools. If more than one vendor has been preselected, resultant solution results are compared and the optimum solution is selected.

摘要翻译： 用于优化通常由软件工具解决的复杂问题的解决方案的方法和结构包括将问题数据选择性地转换成适合于一个或多个预选供应商的解决方案工具集合的格式，并将格式化的设计数据输入到一个或多个预先选择的供应商集合 的解决方案工具。 如果预先选择了多个供应商，则比较所得到的解决方案结果并选择最佳解决方案。

公开(公告)号：US06836849B2

公开(公告)日：2004-12-28

申请号：US09826986

申请日：2001-04-05

申请人： Bishop Chapman Brock ,  Harm Peter Hofstee ,  Mark A. Johnson ,  Thomas Walter Keller, Jr. ,  Kevin John Nowka

发明人： Bishop Chapman Brock ,  Harm Peter Hofstee ,  Mark A. Johnson ,  Thomas Walter Keller, Jr. ,  Kevin John Nowka

IPC分类号： G06F126

CPC分类号： G06F1/3203

摘要： A method and controller for managing power and performance of a multiprocessor (MP) system is described. The controller receives sensor data corresponding to physical parameters within the MP system. The controller also receives quality of service and policy parameters corresponding to the MP system. The quality of service parameters define commitments to customers for utilization of the MP system. The policy parameters correspond to operation limits on inputs and outputs of the MP system. The operation input limits relate to the cost and availability of power or individual processor availability. The operation output limits relate to the amount of heat, acoustic noise levels, EMC levels, etc. that the individual or group of processors in the MP system are allowed to generate in a particular environment. A controller receives the physical parameters, the quality of service parameters and policy parameters and determines performance goals for the MP system and processors within the MP system. Then controller generates controls and applies them to individual processors to achieve the performance goals.

摘要翻译： 描述了一种用于管理多处理器（MP）系统的功率和性能的方法和控制器。 控制器接收与MP系统内的物理参数对应的传感器数据。 控制器还接收与MP系统对应的服务质量和策略参数。 服务质量参数定义了对客户使用MP系统的承诺。 策略参数对应于MP系统的输入和输出的操作限制。 操作输入限制涉及功率或单个处理器可用性的成本和可用性。 操作输出限制涉及允许MP系统中的个体或一组处理器在特定环境中生成的热量，声学噪声水平，EMC等级等。 控制器接收物理参数，服务质量参数和策略参数，并确定MP系统中的MP系统和处理器的性能目标。 然后控制器生成控件并将其应用于各个处理器以实现性能目标。

公开(公告)号：US06779049B2

公开(公告)日：2004-08-17

申请号：US09736585

申请日：2000-12-14

申请人： Erik R. Altman ,  Peter G. Capek ,  Michael Gschwind ,  Harm Peter Hofstee ,  James Allan Kahle ,  Ravi Nair ,  Sumedh Wasudeo Sathaye ,  John-David Wellman ,  Masakazu Suzuoki ,  Takeshi Yamazaki

发明人： Erik R. Altman ,  Peter G. Capek ,  Michael Gschwind ,  Harm Peter Hofstee ,  James Allan Kahle ,  Ravi Nair ,  Sumedh Wasudeo Sathaye ,  John-David Wellman ,  Masakazu Suzuoki ,  Takeshi Yamazaki

IPC分类号： G06F1328

CPC分类号： G06F12/1027 ,  G06F2212/682

摘要： A method and system for attached processing units accessing a shared memory in an SMP system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of processing elements coupled to the shared memory. Each of the plurality of processing elements comprises a processing unit, a direct memory access controller and a plurality of attached processing units. Each direct memory access controller comprises an address translation mechanism thereby enabling each associated attached processing unit to access the shared memory in a restricted manner without an address translation mechanism. Each attached processing unit is configured to issue a request to an associated direct memory access controller to access the shared memory specifying a range of addresses to be accessed as virtual addresses. The associated direct memory access controller is configured to translate the range of virtual addresses into an associated range of physical addresses.

摘要翻译： 用于在SMP系统中访问共享存储器的附加处理单元的方法和系统。 在一个实施例中，系统包括共享存储器。 该系统还包括耦合到共享存储器的多个处理元件。 多个处理单元中的每一个包括处理单元，直接存储器存取控制器和多个附加的处理单元。 每个直接存储器访问控制器包括地址转换机制，从而使得每个相关联的附属处理单元能够以无限制的方式访问共享存储器，而无需地址转换机制。 每个附加的处理单元被配置为向相关联的直接存储器访问控制器发出请求以访问指定要作为虚拟地址访问的地址范围的共享存储器。 相关联的直接存储器访问控制器被配置为将虚拟地址的范围转换为相关的物理地址范围。

公开(公告)号：US06717882B1

公开(公告)日：2004-04-06

申请号：US10273590

申请日：2002-10-17

申请人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Shoji Onishi ,  Osamu Takahashi

发明人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Shoji Onishi ,  Osamu Takahashi

IPC分类号： G11C800

CPC分类号： G11C8/16

摘要： An improved cell circuit for data readout for use in a multiport memory is provided. The multiport memory stores write data signals. The cell circuit includes a plurality of multiplexers each coupled to a discharge device. Each of the multiplexers receives a subset of the write data signals and a plurality of read wordline signals and selects an output enable signal among the subset of the write data signals based on the read wordline signals. Each of the discharge devices are coupled to one of the multiplexers for receiving the output enable signal to generate a drive signal for driving one or more bitlines of the multiport memory.

摘要翻译： 提供用于多端口存储器中的用于数据读出的改进的单元电路。 多端口存储器存储写入数据信号。 电池电路包括多个多路复用器，每个多路复用器耦合到放电装置。 每个多路复用器接收写入数据信号的子集和多个读取字线信号，并且基于所读取的字线信号在写入数据信号的子集中选择输出使能信号。 每个放电装置耦合到多路复用器中的一个，用于接收输出使能信号，以产生用于驱动多端口存储器的一个或多个位线的驱动信号。

公开(公告)号：US06600959B1

公开(公告)日：2003-07-29

申请号：US09498934

申请日：2000-02-04

申请人： Paula Kristine Coulman ,  Sang Hoo Dhong ,  Brian King Flachs ,  Harm Peter Hofstee ,  Jaehong Park ,  Stephen Douglas Posluszny ,  Joel Abraham Silberman ,  Osamu Takahashi

发明人： Paula Kristine Coulman ,  Sang Hoo Dhong ,  Brian King Flachs ,  Harm Peter Hofstee ,  Jaehong Park ,  Stephen Douglas Posluszny ,  Joel Abraham Silberman ,  Osamu Takahashi

IPC分类号： G05B1918

CPC分类号： H03K17/693 ,  H03K5/06

摘要： A method and apparatus for using dynamic programmable logic arrays in microprocessor control logic provide decreased power and increased clock frequencies for data processing systems, by using programmable logic arrays exclusively for the control logic. The method and apparatus further simplify the design of the control logic and closure of timing within the microprocessor, by providing overlap of control logic evaluations and data transfers within the microprocessor.

摘要翻译： 在微处理器控制逻辑中使用动态可编程逻辑阵列的方法和装置通过专门用于控制逻辑的可编程逻辑阵列来为数据处理系统提供降低的功率和增加的时钟频率。 该方法和装置通过在微处理器内提供控制逻辑评估和数据传输的重叠来进一步简化控制逻辑的设计和微处理器内的定时闭合。

公开(公告)号：US09703516B2

公开(公告)日：2017-07-11

申请号：US13269583

申请日：2011-10-08

申请人： Harm Peter Hofstee ,  Charles Ray Johns ,  James Allan Kahle

发明人： Harm Peter Hofstee ,  Charles Ray Johns ,  James Allan Kahle

IPC分类号： G06F3/00 ,  G06F3/14 ,  G09G5/14

CPC分类号： G06F3/1423 ,  G06F3/1454 ,  G09G5/14 ,  G09G2360/121 ,  G09G2370/04

摘要： A flexible input/output controller logic interfaces with existing input/output controllers (IOC's) in order to configure the amount of data sent to and received from the IOC's. The flexible I/O interface receives data from a component at a rate determined by the particular component. The flexible I/O interface then feeds the received data to a traditional I/O controller at a rate suitable for the I/O controller. Thus, the interface to the individual I/O controllers is maintained. The flexible I/O logic balances bandwidth between a plurality of individual I/O controllers in order to better utilize the overall system I/O bandwidth. In one embodiment, the I/O configuration managed by the flexible I/O logic is determined during system-build, while in another embodiment, the I/O configuration is set during system initialization.

公开(公告)号：US08295056B2

公开(公告)日：2012-10-23

申请号：US12507591

申请日：2009-07-22

申请人： Paul Stephen Andry ,  Harm Peter Hofstee ,  George A. Katopis ,  John Ulrich Knickerbocker ,  Robert K. Montoye ,  Chirag S. Patel

发明人： Paul Stephen Andry ,  Harm Peter Hofstee ,  George A. Katopis ,  John Ulrich Knickerbocker ,  Robert K. Montoye ,  Chirag S. Patel

IPC分类号： H05K7/00

CPC分类号： H01L25/0655 ,  H01L23/147 ,  H01L23/60 ,  H01L25/0652 ,  H01L2224/16225 ,  H01L2924/10253 ,  H01L2924/157 ,  Y02T10/82 ,  H01L2924/00

摘要： A silicon carrier structure for electronic packaging includes a base substrate, a silicon carrier substrate disposed on the base substrate, a memory chip disposed on the silicon carrier substrate, a microprocessor chip disposed on the silicon carrier substrate, an input/output chip disposed on the silicon carrier substrate, and a clocking chip disposed on the silicon carrier substrate.

摘要翻译： 一种用于电子封装的硅载体结构包括基底，设置在基底基板上的硅载体衬底，设置在硅载体衬底上的存储芯片，设置在硅载体衬底上的微处理器芯片，设置在硅衬底上的输入/输出芯片 硅载体衬底和设置在硅载体衬底上的时钟芯片。

公开(公告)号：US08229989B2

公开(公告)日：2012-07-24

申请号：US12238500

申请日：2008-09-26

申请人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Christian Jacobi ,  Silvia Melitta Mueller ,  Hwa-Joon Oh

发明人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Christian Jacobi ,  Silvia Melitta Mueller ,  Hwa-Joon Oh

IPC分类号： G06F7/38

CPC分类号： G06F7/49947 ,  G06F7/483 ,  G06F7/49968 ,  G06F7/49973 ,  G06F7/49989 ,  G06F2207/3828

摘要： A method for controlling rounding modes in a single instruction multiple data (SIMD) floating-point unit is disclosed. The SIMD floating-point unit includes a floating-point status-and-control register (FPSCR) having a first rounding mode bit field and a second rounding mode bit field. The SIMD floating-point unit also includes means for generating a first slice and a second slice. During a floating-point operation, the SIMD floating-point unit concurrently performs a first rounding operation on the first slice and a second rounding operation on the second slice according to a bit in the first rounding mode bit field and a bit in the second rounding mode bit field within the FPSCR, respectively.

摘要翻译： 公开了一种用于在单指令多数据（SIMD）浮点单元中控制舍入模式的方法。 SIMD浮点单元包括具有第一舍入模式位字段和第二舍入模式位字段的浮点状态和控制寄存器（FPSCR）。 SIMD浮点单元还包括用于生成第一切片和第二切片的装置。 在浮点运算期间，SIMD浮点单元根据第一舍入模式位字段中的位并且在第二舍入中的位同时对第一切片进行第一舍入运算，并对第二切片进行第二舍入运算 FPSCR中的模式位字段。

公开(公告)号：US20120030386A1

公开(公告)日：2012-02-02

申请号：US13269583

申请日：2011-10-08

申请人： Harm Peter Hofstee ,  Charles Ray Johns ,  James Allan Kahle

发明人： Harm Peter Hofstee ,  Charles Ray Johns ,  James Allan Kahle

IPC分类号： G06F13/36

CPC分类号： G06F3/1423 ,  G06F3/1454 ,  G09G5/14 ,  G09G2360/121 ,  G09G2370/04

摘要： A flexible input/output controller logic interfaces with existing input/output controllers (IOC's) in order to configure the amount of data sent to and received from the IOC's. The flexible I/O interface receives data from a component at a rate determined by the particular component. The flexible I/O interface then feeds the received data to a traditional I/O controller at a rate suitable for the I/O controller. Thus, the interface to the individual I/O controllers is maintained. The flexible I/O logic balances bandwidth between a plurality of individual I/O controllers in order to better utilize the overall system I/O bandwidth. In one embodiment, the I/O configuration managed by the flexible I/O logic is determined during system-build, while in another embodiment, the I/O configuration is set during system initialization.

摘要翻译： 灵活的输入/输出控制器逻辑与现有的输入/输出控制器（IOC）进行接口，以便配置向国际奥委会发送和接收的数据量。 灵活的I / O接口以特定组件确定的速率从组件接收数据。 然后，灵活的I / O接口以适合于I / O控制器的速率将接收的数据馈送到传统的I / O控制器。 因此，保持与各个I / O控制器的接口。 灵活的I / O逻辑平衡多个独立I / O控制器之间的带宽，以便更好地利用整个系统I / O带宽。 在一个实施例中，在系统构建期间确定由灵活I / O逻辑管理的I / O配置，而在另一实施例中，在系统初始化期间设置I / O配置。