公开(公告)号：US06812119B1

公开(公告)日：2004-11-02

申请号：US10614052

申请日：2003-07-08

Applicant: Shibly S. Ahmed ,  Ming-Ren Lin ,  Haihong Wang ,  Bin Yu

Inventor： Shibly S. Ahmed ,  Ming-Ren Lin ,  Haihong Wang ,  Bin Yu

IPC: H01L213205

CPC classification number: H01L29/785 ,  H01L29/66818 ,  H01L29/7842

Abstract: A method of forming fins for a double-gate fin field effect transistor (FinFET) includes forming a second layer of semi-conducting material over a first layer of semi-conducting material and forming double caps in the second layer of semi-conducting material. The method further includes forming spacers adjacent sides of each of the double caps and forming double fins in the first layer of semi-conducting material beneath the double caps. The method also includes thinning the double fins to produce narrow double fins.

Abstract translation: 一种形成双栅极鳍效应晶体管（FinFET）的鳍片的方法包括在第一半导体材料层上形成第二半导电材料层，并在第二半导体材料层中形成双重盖子。 该方法还包括在每个双盖的侧面上形成间隔物，并在双重帽下面的第一半导体材料层中形成双翅片。 该方法还包括使双翅片变薄以产生窄的双翅片。

公开(公告)号：US06362055B1

公开(公告)日：2002-03-26

申请号：US09144527

申请日：1998-08-31

Applicant: Ming-Ren Lin ,  Bin Yu

Inventor： Ming-Ren Lin ,  Bin Yu

IPC: H01L218234

Abstract: A semiconductor device includes a first gate stack and a second gate stack, each gate stack corresponding to a gate of a FET formed on the semiconductor device. The first gate stack includes a gate material formed from one of poly-silicon, poly-SiGe, and amorphous silicon. The gate material is implanted with a dopant of a first conductivity type at a first concentration. A metal silicide layer is formed over the doped gate material. The second gate stack includes a gate material formed from one of poly-silicon, poly-Si—Ge, and amorphous silicon. The gate material of the second gate stack is implanted with a dopant of a second conductivity type at a second concentration.

公开(公告)号：US06225661B1

公开(公告)日：2001-05-01

申请号：US09145786

申请日：1998-09-02

Applicant: Judy Xilin An ,  Bin Yu ,  Ming-Ren Lin

Inventor： Judy Xilin An ,  Bin Yu ,  Ming-Ren Lin

IPC: H01L27088

CPC classification number: H01L21/28194 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545 ,  H01L2924/0002 ,  Y10S257/90 ,  Y10S438/981 ,  H01L2924/00

Abstract: A field effect transistor (FET) is formed on a silicon substrate, with a nitride gate insulator layer being deposited on the substrate and an oxide gate insulator layer being deposited on the nitride layer to insulate a gate electrode from source and drain regions in the substrate. The gate material is then removed to establish a gate void, and spacers are deposited on the sides of the void such that only a portion of the oxide layer is covered by the spacers. Then, the unshielded portion of the oxide layer is removed, thus establishing a step between the oxide and nitride layers that overlays the source and drain extensions under the gate void to reduce subsequent capacitive coupling and charge carrier tunneling between the gate and the extensions. The spacers are removed and the gate void is refilled with gate electrode material.

Abstract translation: 在硅衬底上形成场效应晶体管（FET），其中氮化物栅极绝缘体层沉积在衬底上，并且氧化物栅极绝缘体层沉积在氮化物层上以使栅电极与衬底中的源极和漏极区域绝缘 。 然后去除栅极材料以建立栅极空隙，并且间隔物沉积在空隙的侧面上，使得只有一部分氧化物层被间隔物覆盖。 然后，去除氧化物层的非屏蔽部分，从而在栅极空隙下的源极和漏极延伸层之间建立氧化物层和氮化物层之间的步骤，以减少栅极和延伸部之间的后续电容耦合和电荷载流子隧道。 去除间隔物，并用栅电极材料重新填充栅极空隙。

公开(公告)号：US06190980B1

公开(公告)日：2001-02-20

申请号：US09150874

申请日：1998-09-10

Applicant: Bin Yu ,  Ming-Ren Lin ,  Emi Ishida

Inventor： Bin Yu ,  Ming-Ren Lin ,  Emi Ishida

IPC: H01L21336

CPC classification number: H01L29/66583 ,  H01L21/26586 ,  H01L29/66492 ,  H01L29/66537

Abstract: A method of performing tilted implantation for pocket, halo and source/drain extensions in ULSI dense structures. The method overcomes the process limit, due to shadowing effects, in dense structures, of using large angle tilted implant techniques in ULSI circuits. A gate opening in an oxide layer is defined and partially filled by insertion of nitride spacers to define an actual gate window opening. The small angle tilted implant technique has the equivalent doping effect of large angle tilted implants, and circumvents the maximum angle limit (&thgr;MAX) that occurs in the large angle implant method. The small angle tilted implant technique also automatically provides self alignment of the pocket/halo/extension implant to the gate of the device.

Abstract translation: 在ULSI致密结构中进行凹槽，晕圈和源极/漏极延伸的倾斜注入的方法。 该方法克服了在密集结构中的阴影效应，在ULSI电路中使用大角度倾斜植入技术的过程极限。 通过插入氮化物间隔物限定氧化层中的开口，并且通过插入氮化物间隔物来部分地填充以限定实际的门窗开口。 小角度倾斜植入技术具有大角度倾斜植入物的等效掺杂效应，并避开了大角度植入法中发生的最大角度限制（thetaMAX）。 小角度倾斜植入技术还自动提供袋/晕/延伸植入物到装置的门的自对准。

公开(公告)号：US08222680B2

公开(公告)日：2012-07-17

申请号：US10274961

申请日：2002-10-22

Applicant: Ming-Ren Lin ,  Judy Xilin An ,  Zoran Krivokapic ,  Cyrus E. Tabery ,  Haihong Wang ,  Bin Yu

Inventor： Ming-Ren Lin ,  Judy Xilin An ,  Zoran Krivokapic ,  Cyrus E. Tabery ,  Haihong Wang ,  Bin Yu

IPC: H01L29/72

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/66818

Abstract: A double gate metal-oxide semiconductor field-effect transistor (MOSFET) includes a fin, a first gate and a second gate. The first gate is formed on top of the fin. The second gate surrounds the fin and the first gate. In another implementation, a triple gate MOSFET includes a fin, a first gate, a second gate, and a third gate. The first gate is formed on top of the fin. The second gate is formed adjacent the fin. The third gate is formed adjacent the fin and opposite the second gate.

Abstract translation: 双栅极金属氧化物半导体场效应晶体管（MOSFET）包括鳍状物，第一栅极和第二栅极。 第一个门形成在鳍的顶部。 第二个门围绕翅片和第一个门。 在另一实施方案中，三栅极MOSFET包括鳍片，第一栅极，第二栅极和第三栅极。 第一个门形成在鳍的顶部。 第二个门形成在翅片附近。 第三栅极形成在翅片附近并与第二栅极相对。

公开(公告)号：US07416925B2

公开(公告)日：2008-08-26

申请号：US11677404

申请日：2007-02-21

Applicant: Ming-Ren Lin ,  Bin Yu

Inventor： Ming-Ren Lin ,  Bin Yu

IPC: H01L21/00

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/78687

Abstract: A semiconductor device includes a substrate and an insulating layer on the substrate. The semiconductor device also includes a fin structure formed on the insulating layer, where the fin structure includes first and second side surfaces, a dielectric layer formed on the first and second side surfaces of the fin structure, a first gate electrode formed adjacent the dielectric layer on the first side surface of the fin structure, a second gate electrode formed adjacent the dielectric layer on the second side surface of the fin structure, and a doped structure formed on an upper surface of the fin structure in the channel region of the semiconductor device.

Abstract translation: 半导体器件包括衬底和衬底上的绝缘层。 半导体器件还包括形成在绝缘层上的翅片结构，其中鳍结构包括第一和第二侧表面，形成在鳍结构的第一和第二侧表面上的电介质层，形成在电介质层附近的第一栅电极 在翅片结构的第一侧表面上形成与鳍结构的第二侧表面上的电介质层相邻的第二栅电极，以及在半导体器件的沟道区中形成在鳍结构的上表面上的掺杂结构 。

公开(公告)号：US07250645B1

公开(公告)日：2007-07-31

申请号：US10761374

申请日：2004-01-22

Applicant: Haihong Wang ,  Shibly S. Ahmed ,  Ming-Ren Lin ,  Bin Yu

Inventor： Haihong Wang ,  Shibly S. Ahmed ,  Ming-Ren Lin ,  Bin Yu

IPC: H01L29/76 ,  H01L27/08

CPC classification number: H01L29/785 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/7842

Abstract: A fin field effect transistor (FinFET) includes a reversed T-shaped fin. The FinFET further includes source and drain regions formed adjacent the reversed T-shaped fin. The FinFET further includes a dielectric layer formed adjacent surfaces of the fin and a gate formed adjacent the dielectric layer.

Abstract translation: 翅片场效应晶体管（FinFET）包括反转的T形翅片。 FinFET还包括邻近反转的T形翅片形成的源极和漏极区域。 FinFET还包括邻近散热片表面形成的电介质层和邻近电介质层形成的栅极。

公开(公告)号：US06852576B2

公开(公告)日：2005-02-08

申请号：US10825175

申请日：2004-04-16

Applicant: Ming-Ren Lin ,  Haihong Wang ,  Bin Yu

Inventor： Ming-Ren Lin ,  Haihong Wang ,  Bin Yu

IPC: H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/786 ,  H01L21/84

CPC classification number: H01L29/785 ,  H01L21/823412 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/66795 ,  H01L29/7842

Abstract: A method forms fin structures for a semiconductor device. The method includes forming a first fin structure including a dielectric material and including a first side surface and a second side surface; forming a second fin structure adjacent the first side surface of the first fin structure; and forming a third fin structure adjacent the second side surface of the first fin structure. The second fin structure and the third fin structure are formed of a different material than the first fin structure.

Abstract translation: 一种形成半导体器件的鳍结构的方法。 该方法包括形成包括电介质材料并包括第一侧表面和第二侧表面的第一鳍结构; 在所述第一翅片结构的第一侧表面附近形成第二鳍结构; 以及在所述第一翅片结构的所述第二侧表面附近形成第三鳍​​结构。 第二翅片结构和第三翅片结构由与第一翅片结构不同的材料形成。

公开(公告)号：US06380019B1

公开(公告)日：2002-04-30

申请号：US09187498

申请日：1998-11-06

Applicant: Bin Yu ,  Ming-Ren Lin ,  Shekhar Pramanick

Inventor： Bin Yu ,  Ming-Ren Lin ,  Shekhar Pramanick

IPC: H01L2976

CPC classification number: H01L21/74 ,  H01L29/0649 ,  H01L29/6659

Abstract: A thin filmed fully-depleted silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) utilizes a local insulation structure. The local insulative structure includes a buried silicon dioxide region under the channel region. The MOSFET body thickness is very small and yet silicon available outside of the channel region and buried silicon dioxide region is available for sufficient depths of silicide in the source and drain regions. The buried silicon dioxide region can be formed by a trench isolation technique or a LOCOS technique.

Abstract translation: 薄膜完全耗尽的绝缘体上硅（SOI）金属氧化物半导体场效应晶体管（MOSFET）利用局部绝缘结构。 局部绝缘结构包括沟道区下方的埋置二氧化硅区域。 MOSFET体的厚度非常小，而在沟道区域和掩埋的二氧化硅区域之外可用的硅可用于源极和漏极区域中足够的硅化物深度。 掩埋的二氧化硅区域可以通过沟槽隔离技术或LOCOS技术形成。

公开(公告)号：US06281555B1

公开(公告)日：2001-08-28

申请号：US09187861

申请日：1998-11-06

Applicant: Bin Yu ,  Ming-Ren Lin

Inventor： Bin Yu ,  Ming-Ren Lin

IPC: H01K2976

CPC classification number: H01L21/76237 ,  H01L21/26506 ,  H01L21/2658

Abstract: An integrated circuit is provided having an improved packing density due to an improved isolation structure between a plurality of devices on the substrate. An ultra shallow trench isolation structure is provided, typically having a trench depth just deeper than the doped regions of a transistor or other device placed thereon, but substantially shallower than the depth of a well associated with the transistor. A nitrogen ion implantation step is utilized to fabricate an implanted portion beneath the insulative portion, the implanted portion extending preferably below the depth of the well. Due to a shallower trench isolation structure, the structure may also be narrower, providing for improved packing density in a semiconductor device.

Abstract translation: 提供了一种集成电路，由于衬底上的多个器件之间的改进的隔离结构而具有改进的封装密度。 提供了一种超浅沟槽隔离结构，其通常具有刚好比放置在其上的晶体管或其它器件的掺杂区域更深的沟槽深度，但是基本上比与晶体管相关联的阱的深度浅。 使用氮离子注入步骤来制造在绝缘部分下方的植入部分，所述注入部分优选地延伸到井的深度之下。 由于较浅的沟槽隔离结构，结构也可能更窄，从而提供了半导体器件中改善的封装密度。