Methods of forming fin field effect transistors using oxidation barrier layers and related devices
    23.
    发明申请
    Methods of forming fin field effect transistors using oxidation barrier layers and related devices 有权
    使用氧化阻挡层和相关器件形成鳍式场效应晶体管的方法

    公开(公告)号:US20050272192A1

    公开(公告)日:2005-12-08

    申请号:US11020899

    申请日:2004-12-23

    摘要: A method of forming a fin field effect transistor on a semiconductor substrate includes forming a fin-shaped active region vertically protruding from the substrate. An oxide layer is formed on a top surface and opposing sidewalls of the fin-shaped active region. An oxidation barrier layer is formed on the opposing sidewalls of the fin-shaped active region and is planarized to a height no greater than about a height of the oxide layer to form a fin structure. The fin structure is oxidized to form a capping oxide layer on the top surface of the fin-shaped active region and to form at least one curved sidewall portion proximate the top surface of the fin-shaped active region. The oxidation barrier layer has a height sufficient to reduce oxidation on the sidewalls of the fin-shaped active region about halfway between the top surface and a base of the fin-shaped active region. Related devices are also discussed.

    摘要翻译: 在半导体衬底上形成鳍状场效应晶体管的方法包括形成从衬底垂直突出的鳍状有源区。 在鳍状有源区的上表面和相对侧壁上形成氧化物层。 在翅片状有源区域的相对的侧壁上形成氧化阻挡层,并将其平坦化至不大于氧化物层高度的高度以形成翅片结构。 翅片结构被氧化以在翅片形有源区的顶表面上形成封盖氧化层,并且在翅片形有源区的顶表面附近形成至少一个弯曲的侧壁部分。 氧化阻挡层的高度足以减小翅片形有源区的侧壁上的氧化,大约在鳍状有源区的顶表面和基底之间的一半处。 还讨论了相关设备。

    Memory devices and methods of operating the same
    25.
    发明授权
    Memory devices and methods of operating the same 有权
    内存设备及操作方法

    公开(公告)号:US09418739B2

    公开(公告)日:2016-08-16

    申请号:US14616806

    申请日:2015-02-09

    IPC分类号: G11C11/00 G11C13/00 G11C11/56

    摘要: Methods of operating a memory device include; applying a first set write voltage to a selected first signal line connected to a selected memory cell, applying a first inhibition voltage to non-selected first signal lines connected to non-selected memory cells, and controlling a first voltage of a selected second signal line connected to the selected memory cell to be less than the first set write voltage, and a difference between the first inhibition voltage and the first voltage is less than a threshold voltage of the selection element.

    摘要翻译: 操作存储设备的方法包括: 对连接到所选择的存储单元的所选择的第一信号线施加第一组写入电压,向连接到未选择的存储器单元的未选择的第一信号线施加第一抑制电压,以及控制所选择的第二信号线的第一电压 连接到所选择的存储单元以小于第一设置写入电压,并且第一抑制电压和第一电压之间的差小于选择元件的阈值电压。

    Electrically Erasable Programmable Read-Only Memory (EEPROM) Cell and Methods for Forming and Reading the Same
    26.
    发明申请
    Electrically Erasable Programmable Read-Only Memory (EEPROM) Cell and Methods for Forming and Reading the Same 有权
    电可擦除可编程只读存储器(EEPROM)单元及其形成和读取方法

    公开(公告)号:US20110038210A1

    公开(公告)日:2011-02-17

    申请号:US12912517

    申请日:2010-10-26

    IPC分类号: G11C16/26 G11C16/04 G11C16/30

    摘要: In a method of reading data in an EEPROM cell, a bit line voltage for reading is applied to the EEPROM cell including a memory transistor and a selection transistor. A first voltage is applied to a sense line of the memory transistor. A second voltage greater than the first voltage is applied to a word line of the selection transistor. A current passing through the EEPROM cell is compared with a predetermined reference current to read the data stored in the EEPROM cell. An on-cell current of the EEPROM cell may be increased in an erased state and the data in the cell may be readily discriminated.

    摘要翻译: 在EEPROM单元中读取数据的方法中,用于读取的位线电压被施加到包括存储晶体管和选择晶体管的EEPROM单元。 第一电压被施加到存储晶体管的感测线。 大于第一电压的第二电压被施加到选择晶体管的字线。 将通过EEPROM单元的电流与预定的参考电流进行比较,以读取存储在EEPROM单元中的数据。 可以在擦除状态下增加EEPROM单元的通电池电流,并且可以容易地区分单元中的数据。

    Mask ROM and method of fabricating the same
    27.
    发明授权
    Mask ROM and method of fabricating the same 有权
    掩模ROM及其制造方法

    公开(公告)号:US07638387B2

    公开(公告)日:2009-12-29

    申请号:US11823381

    申请日:2007-06-27

    IPC分类号: H01L21/8234

    CPC分类号: H01L27/1021

    摘要: A mask read-only memory (ROM) includes a dielectric layer formed on a substrate and a plurality of first conductive lines formed on the dielectric layer. A plurality of diodes are formed in the first conductive lines, and a plurality of final vias are formed for a first set of the diodes each representing a first type of memory cell, with no final via being formed for a second set of diodes each representing a second type of memory cell. Each of a plurality of second conductive lines is formed over a column of the diodes.

    摘要翻译: 掩模只读存储器(ROM)包括形成在基板上的电介质层和形成在电介质层上的多个第一导电线。 在第一导线中形成多个二极管,并且为第一组二极管形成多个最终通孔,每个二极管表示第一类型的存储单元,没有形成用于第二组二极管的最终通孔,每个二极管表示 第二种类型的存储单元。 多个第二导电线中的每一个形成在二极管的列上。