公开(公告)号：US6090656A

公开(公告)日：2000-07-18

申请号：US74837

申请日：1998-05-08

申请人： Todd A. Randazzo

发明人： Todd A. Randazzo

IPC分类号： H01L21/02 ,  H01L27/06 ,  H01L21/8242

CPC分类号： H01L27/0629 ,  H01L28/60

摘要： A capacitor that is a metal to polysilicon capacitor. The capacitor is fabricated by forming a field oxide layer on a substrate. Then, a polysilicon segment is formed on the field oxide layer. This polysilicon segment forms a polysilicon bottom plate for the capacitor. A dielectric layer is formed and planarized. An opening is made in the dielectric layer to expose a portion of the polysilicon segment. Then, an oxide layer is formed on exposed portions of the polysilicon segment. A metal segment is formed on the oxide layer over the opening, wherein the metal segment forms a top-plate for the semiconductor device.

公开(公告)号：US5821572A

公开(公告)日：1998-10-13

申请号：US768905

申请日：1996-12-17

申请人： John D. Walker ,  Todd A. Randazzo ,  Gayle W. Miller

发明人： John D. Walker ,  Todd A. Randazzo ,  Gayle W. Miller

IPC分类号： H01L27/02 ,  H01L29/74 ,  H01L31/111

CPC分类号： H01L27/0262

摘要： The present invention provides a semiconductor protection device in a substrate having a first type of conductivity. The semiconductor protection device includes two vertical bipolar transistors. A well region is located within the substrate having a second type of conductivity with a base region within the well region having a first type of conductivity. A first doped region having the second type of conductivity and a second doped region having a first type of conductivity are located within the well region. A third doped region having the second type of conductivity and a fourth doped region having the first type of conductivity are located within the base region. A doped region having a first type of conductivity is located within the substrate. This doped region is connected to the fourth doped region.

摘要翻译： 本发明提供了具有第一类导电性的衬底中的半导体保护器件。 半导体保护器件包括两个垂直双极晶体管。 阱区位于衬底内，具有第二类导电性，阱区内具有第一类导电性。 具有第二类型导电性的第一掺杂区域和具有第一类型导电性的第二掺杂区域位于阱区域内。 具有第二类型导电性的第三掺杂区域和具有第一类型导电性的第四掺杂区域位于基极区域内。 具有第一类型导电性的掺杂区域位于衬底内。 该掺杂区域连接到第四掺杂区域。

公开(公告)号：US07457090B2

公开(公告)日：2008-11-25

申请号：US10988122

申请日：2004-11-12

申请人： Todd A. Randazzo

发明人： Todd A. Randazzo

IPC分类号： H02H3/20 ,  H02H9/04

CPC分类号： H03F1/52

摘要： A method and apparatus are provided for protecting elements of a receiver from overvoltages in a pseudo-differential signal having a true signal and a reference voltage. The method and apparatus limit the true signal to a protection voltage, which is correlated to the reference voltage, to produce a protected true signal. The protected true signal and the reference voltage are applied to inputs of the receiver.

摘要翻译： 提供了一种方法和装置，用于在具有真实信号和参考电压的伪差分信号中保护接收器的元件免受过电压。 该方法和装置将真实信号限制为与参考电压相关的保护电压，以产生受保护的真实信号。 受保护的真实信号和参考电压被施加到接收器的输入。

公开(公告)号：US06710990B2

公开(公告)日：2004-03-23

申请号：US10055082

申请日：2002-01-22

申请人： John de Q. Walker ,  Todd A. Randazzo

发明人： John de Q. Walker ,  Todd A. Randazzo

IPC分类号： H02H904

CPC分类号： H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

摘要： As technology in the semiconductor industry advances, semiconductor devices decrease in size to become faster and less expensive per function. Smaller semiconductor devices, particularly MOSFETs, are increasingly sensitive to Electrostatic Discharge (ESD). ESD can either destroy or permanently damage a semiconductor device. Embodiments of the present invention assist in preventing ESD damage to semiconductor devices. An embodiment of the present invention utilizes a diode connected to the substrate terminal of a MOSFET. Under normal operation up to the maximum operating voltage, the diode and MOS devices are open and do not conduct. The diode triggers when an ESD pulse causes the reverse breakdown voltage of the diode to be exceeded. The resultant current switches a connected MOS device, operating in bipolar mode, to dissipate the damaging ESD pulse. The ESD pulse is shunted to ground, thereby avoiding damage to the rest of the device.

摘要翻译： 随着半导体行业的技术进步，半导体器件的尺寸减小，每个功能变得更快，成本更低。 较小的半导体器件，尤其是MOSFET，对静电放电（ESD）越来越敏感。 ESD可以破坏或永久性地损坏半导体器件。 本发明的实施例有助于防止对半导体器件的ESD损伤。 本发明的实施例利用连接到MOSFET的衬底端子的二极管。 在正常工作下，最高工作电压，二极管和MOS器件都是开放的，不会导通。 当ESD脉冲导致二极管的反向击穿电压超过时，二极管触发。 所产生的电流切换连接的MOS器件，以双极模式工作，以消散有害的ESD脉冲。 ESD脉冲分流到地，从而避免损坏设备的其余部分。

公开(公告)号：US06225178B1

公开(公告)日：2001-05-01

申请号：US07466709

申请日：1990-01-02

申请人： Gordon A. Shaw ,  Curtis H. Rahn ,  Cheisan Yue ,  Todd A. Randazzo

发明人： Gordon A. Shaw ,  Curtis H. Rahn ,  Cheisan Yue ,  Todd A. Randazzo

IPC分类号： H01L21336

CPC分类号： H01L21/76216

摘要： A process for oxidizing the silicon layer into a device-isolating field oxide having a radiation-hardened reduced bird's beak. An angled and rotated field implant prior to oxidation is used to increase the doping concentration in the edge region of the MOS transistors to compensate for boron leaching during oxidation. The field oxide is grown at a low temperature by high pressure oxidation which increases total dose hardness by making a silicon-rich oxide film.

摘要翻译： 将硅层氧化成具有辐射硬化的还原鸟喙的装置隔离场氧化物的方法。 在氧化之前使用倾斜和旋转的场注入来增加MOS晶体管的边缘区域中的掺杂浓度，以补偿氧化过程中的硼浸出。 场氧化物通过高压氧化在低温下生长，通过制造富硅氧化物膜来增加总剂量硬度。

公开(公告)号：US06194766B1

公开(公告)日：2001-02-27

申请号：US09495512

申请日：2000-02-01

申请人： Todd A. Randazzo

发明人： Todd A. Randazzo

IPC分类号： H01L2972

CPC分类号： H01L29/66613 ,  H01L21/823462 ,  H01L21/823493 ,  H01L21/823807 ,  H01L27/088 ,  H01L29/42364

摘要： High voltage and low voltage devices are provided on a common semiconductor substrate. An integrated semiconductor circuit includes a semiconductor substrate of a first conductivity type. Well regions of a first conductivity type and well regions of a second conductivity type are formed in the substrate. Low voltage devices are formed in well regions of the first conductivity type. A high voltage device includes source/drain regions of the second conductivity type formed, respectively, in well regions of the second conductivity type, an oxide region disposed on a surface of the substrate located above a region of the substrate that serves as a channel for the high voltage device, and a gate region disposed on the oxide region.

摘要翻译： 在公共半导体衬底上提供高电压和低电压器件。 集成半导体电路包括第一导电类型的半导体衬底。 在衬底中形成第一导电类型的阱区和第二导电类型的阱区。 低电压器件形成在第一导电类型的阱区中。 高电压装置包括分别在第二导电类型的阱区中形成的第二导电类型的源极/漏极区域，设置在位于衬底的表面上的氧化物区域，该氧化物区域位于用作沟道的衬底的区域之上 高电压装置和设置在氧化物区域上的栅极区域。

公开(公告)号：US6063672A

公开(公告)日：2000-05-16

申请号：US245193

申请日：1999-02-05

申请人： Gayle Miller ,  Samuel C. Gioia ,  Todd A. Randazzo

发明人： Gayle Miller ,  Samuel C. Gioia ,  Todd A. Randazzo

IPC分类号： H01L21/8234 ,  H01L27/02 ,  H01L27/092

CPC分类号： H01L27/0266 ,  H01L21/823425 ,  H01L27/0921

摘要： MOS functional devices and electrostatic discharge protection devices are formed on a substrate having a relatively low-resistance area beneath the functional devices to inhibit latch-up of the functional devices and a relatively high resistance area beneath each electrostatic protection device to reduce the snapback holding voltage of each electrostatic discharge protection device.

摘要翻译： MOS功能器件和静电放电保护器件形成在功能器件下面具有相对低电阻区域的衬底上，以阻止功能器件的锁定以及每个静电保护器件下方的相对较高的电阻区域以减小回跳保持电压 的每个静电放电保护装置。

公开(公告)号：US5858828A

公开(公告)日：1999-01-12

申请号：US801668

申请日：1997-02-18

申请人： John J. Seliskar ,  David W. Daniel ,  Todd A. Randazzo

发明人： John J. Seliskar ,  David W. Daniel ,  Todd A. Randazzo

IPC分类号： H01L21/266 ,  H01L21/331 ,  H01L21/74 ,  H01L29/08 ,  H01L21/22 ,  H01L21/265 ,  H01L21/8222

CPC分类号： H01L29/66272 ,  H01L21/266 ,  H01L21/74 ,  H01L29/0821 ,  Y10S438/95

摘要： High energy implantation through varying vertical thicknesses of one or more films is used to form a vertically modulated sub-collector, which simultaneously reduces both the vertical and lateral components of parasitic collector resistance in a vertically integrated bipolar device. The need for a sinker implant or other additional steps to reduce collector resistance is avoided. The necessary processing modifications may be readily integrated into conventional bipolar or BiCMOS process flows.

摘要翻译： 使用通过改变一个或多个膜的垂直厚度的高能量注入来形成垂直调制的子集电极，其同时降低垂直集成的双极器件中的寄生集电极电阻的垂直和侧向分量。 避免了沉降式植入物的需要或其他附加步骤以减少集电极电阻。 必要的处理修改可以容易地集成到传统的双极或BiCMOS工艺流程中。

公开(公告)号：US5838616A

公开(公告)日：1998-11-17

申请号：US723327

申请日：1996-09-30

申请人： Todd A. Randazzo

发明人： Todd A. Randazzo

IPC分类号： H01L29/423 ,  H01L29/788 ,  G11C13/00

CPC分类号： H01L29/7883 ,  H01L29/42324

摘要： An electrically-erasable electrically-programmable read only memory (EEPROM) transistor is programmed and erased by electron tunneling and reduces gate induced drain leakage. The EEPROM transistor comprises a semiconductor substrate having source and drain regions disposed horizontally apart. A floating gate conductor is vertically adjacent to and spaced from the source and drain regions. An insulation layer is disposed between the floating gate conductor and the source and drain regions. A first segment of the insulation layer, which is between the drain region and a minor portion of the floating gate conductor, has a first thickness. A second segment of the insulation layer which is adjacent to the first layer and the remainder on the floating gate conductor, has a second thickness which is substantially greater than the first thickness. A low density diffusion area is defined within a segment of the semiconductor substrate which extends from the drain region, encompasses the first segment of the insulation layer, to underneath a portion of the second segment of the insulation layer.

摘要翻译： 电可擦除电可编程只读存储器（EEPROM）晶体管通过电子隧道编程和擦除，并减少栅极引起的漏极泄漏。 EEPROM晶体管包括具有水平分开设置的源区和漏区的半导体衬底。 浮栅导体垂直邻近并与源区和漏区隔开。 绝缘层设置在浮置栅极导体与源极和漏极区之间。 位于漏极区域和浮置栅极导体的次要部分之间的绝缘层的第一段具有第一厚度。 绝缘层的与第一层相邻的第二段和浮置栅极导体上的其余部分具有基本上大于第一厚度的第二厚度。 低密度扩散区域被限定在半导体衬底的从漏极区域延伸的段内，包围绝缘层的第一段到绝缘层的第二段的一部分的下面。

公开(公告)号：US5661687A

公开(公告)日：1997-08-26

申请号：US720601

申请日：1996-03-30

申请人： Todd A. Randazzo

发明人： Todd A. Randazzo

IPC分类号： H01L29/788 ,  G11C13/00

CPC分类号： H01L29/7883

摘要： An electrically programmable floating gate memory cell is gate programmed with tunneling electrons and is not drain erasable. The memory cell comprises a semiconductor substrate, source and drain regions disposed in the semiconductor substrate, a floating gate conductor adjacent to the source and drain regions, a tunnel oxide layer disposed between the floating gate conductor and the source and drain regions, and a control gate conductor adjacent to the floating gate conductor. The source and drain regions each include a high impurity concentration portion and a low impurity concentration portion. The impurity concentration of the low impurity concentration portion is sufficiently low to prevent a substantial threshold voltage variation when a predetermined range of voltages are supplied in a first polarity between the control gate conductor and the drain region.

摘要翻译： 电可编程浮动栅极存储单元是用隧道电子进行栅极编程的，并且不能排除可擦除。 存储单元包括半导体衬底，设置在半导体衬底中的源极和漏极区域，与源极和漏极区域相邻的浮置栅极导体，设置在浮置栅极导体与源极和漏极区域之间的隧道氧化物层，以及控制 栅极导体与浮栅导体相邻。 源区和漏区各自包括高杂质浓度部分和低杂质浓度部分。 低杂质浓度部分的杂质浓度足够低以防止在控制栅极导体和漏极区域之间以第一极性提供预定电压范围时实质的阈值电压变化。