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21.发明申请Split-gate thin film storage NVM cell with reduced load-up/trap-up effects 有权分流栅薄膜存储NVM单元，具有降低的加载/陷阱效应公开(公告)号：US20080188052A1
公开(公告)日：2008-08-07
申请号：US11671809
申请日：2007-02-06
申请人： Brian A. Winstead , Taras A. Kirichenko , Konstantin V. Loiko , Ramachandran Muralidhar , Rajesh A. Rao , Sung-Taeg Kang , Ko-Min Chang , Jane Yater
发明人： Brian A. Winstead , Taras A. Kirichenko , Konstantin V. Loiko , Ramachandran Muralidhar , Rajesh A. Rao , Sung-Taeg Kang , Ko-Min Chang , Jane Yater
IPC分类号： H01L21/336
CPC分类号： H01L29/42332 , H01L21/28273 , H01L29/42328 , H01L29/66825 , H01L29/7885
摘要： A semiconductor process and apparatus are disclosed for forming a split-gate thin film storage NVM device (10) by forming a select gate structure (3) on a first dielectric layer (2) over a substrate (1); forming a control gate structure (6) on a second dielectric layer (5) having embedded nanocrystals (15, 16) so that the control gate (6) is adjacent to the select gate structure (3) but separated therefrom by a gap (8); forming a floating doped region (4) in the substrate (1) below the gap (8) formed between the select gate structure and control gate structure; and forming source/drain regions (11, 12) in the substrate to define a channel region that includes the floating doped region (4).
摘要翻译： 公开了一种半导体工艺和装置，用于通过在衬底（1）上的第一介电层（2）上形成选择栅极结构（3）来形成分裂栅极薄膜存储NVM器件（10）。 在具有嵌入的纳米晶体（15,16）的第二介电层（5）上形成控制栅极结构（6），使得所述控制栅极（6）与所述选择栅极结构（3）相邻，但是通过间隙（8 ）; 在形成在选择栅极结构和控制栅极结构之间的间隙（8）下面的衬底（1）中形成浮置掺杂区（4）; 以及在所述衬底中形成源/漏区（11,12）以限定包括所述浮置掺杂区（4）的沟道区。
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公开(公告)号：US20080150072A1
公开(公告)日：2008-06-26
申请号：US11613326
申请日：2006-12-20
IPC分类号： H01L29/78
CPC分类号： H01L29/0642 , H01L21/823412 , H01L21/84 , H01L27/088 , H01L27/1203 , H01L29/7842 , H01L29/7843 , H01L29/7846 , H01L29/7849
摘要： An integrated circuit includes a device including an active region of the device, where the active region of the device includes a channel region having a transverse and a lateral direction. The device further includes an isolation region adjacent to the active region in a traverse direction from the active region, where the isolation region includes a first region located in a transverse direction to the channel region. The isolation region further includes a second region located in a lateral direction from the first region. The first region of the isolation region is under a stress of a first type and the second region of the isolative region is one of under a lesser stress of the first type or of under a stress of a second type being opposite of the first type.
摘要翻译： 集成电路包括包括器件的有源区的器件，其中器件的有源区包括具有横向和横向方向的沟道区。 器件还包括与有源区相邻的有源区的隔离区，该隔离区位于有源区域的横向方向，其中隔离区域包括位于与沟道区域横向的第一区域。 隔离区域还包括位于从第一区域的横向方向上的第二区域。 隔离区域的第一区域处于第一类型的应力处，并且隔离区域的第二区域是在第一类型的较小应力下或在与第一类型相反的第二类型的应力下的一个区域。
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23.发明申请SEMICONDUCTOR DEVICE INCLUDING AN ACTIVE REGION AND TWO LAYERS HAVING DIFFERENT STRESS CHARACTERISTICS 有权包括活性区域和具有不同应力特性的两层的半导体器件公开(公告)号：US20140054704A1
公开(公告)日：2014-02-27
申请号：US14063459
申请日：2013-10-25
IPC分类号： H01L29/06
CPC分类号： H01L29/0642 , H01L21/823412 , H01L21/84 , H01L27/088 , H01L27/1203 , H01L29/7842 , H01L29/7843 , H01L29/7846 , H01L29/7849
摘要： An integrated circuit includes a device including an active region of the device, where the active region of the device includes a channel region having a transverse and a lateral direction. The device further includes an isolation region adjacent to the active region in a traverse direction from the active region, where the isolation region includes a first region located in a transverse direction to the channel region. The isolation region further includes a second region located in a lateral direction from the first region. The first region of the isolation region is under a stress of a first type and the second region of the isolative region is one of under a lesser stress of the first type or of under a stress of a second type being opposite of the first type.
摘要翻译： 集成电路包括包括器件的有源区的器件，其中器件的有源区包括具有横向和横向方向的沟道区。 器件还包括与有源区相邻的有源区的隔离区，该隔离区位于有源区域的横向方向，其中隔离区域包括位于与沟道区域横向的第一区域。 隔离区域还包括位于从第一区域的横向方向上的第二区域。 隔离区域的第一区域处于第一类型的应力处，并且隔离区域的第二区域是在第一类型的较小应力下或在与第一类型相反的第二类型的应力下。
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公开(公告)号：US07960267B2
公开(公告)日：2011-06-14
申请号：US12414778
申请日：2009-03-31
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28273 , B82Y10/00 , H01L29/42328 , H01L29/7847 , H01L29/7881
摘要： A method of making a semiconductor device on a semiconductor layer includes: forming a gate dielectric over the semiconductor layer; forming a layer of gate material over the gate dielectric; etching the layer of gate material to form a select gate; forming a storage layer that extends over the select gate and over a portion of the semiconductor layer; depositing an amorphous silicon layer over the storage layer; etching the amorphous silicon layer to form a control gate; and annealing the semiconductor device to crystallize the amorphous silicon layer.
摘要翻译： 在半导体层上制造半导体器件的方法包括：在半导体层上形成栅极电介质; 在所述栅极电介质上形成栅极材料层; 蚀刻栅极材料层以形成选择栅极; 形成在所述选择栅极上方和所述半导体层的一部分上方延伸的存储层; 在所述存储层上沉积非晶硅层; 蚀刻非晶硅层以形成控制栅极; 并对半导体器件进行退火以使非晶硅层结晶。
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25.发明授权Method of forming a semiconductor device featuring a gate stressor and semiconductor device 有权形成具有栅极应力和半导体器件的半导体器件的方法公开(公告)号：US07960243B2
公开(公告)日：2011-06-14
申请号：US11756231
申请日：2007-05-31
IPC分类号： H01L21/76 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/823807 , H01L21/26506 , H01L21/823828 , H01L29/7833 , H01L29/7845
摘要： A semiconductor device (10) is formed in a semiconductor layer (12). A gate stack (16,18) is formed over the semiconductor layer and comprises a first conductive layer (22) and a second layer (24) over the first layer. The first layer is more conductive and provides more stopping power to an implant than the second layer. A species (46) is implanted into the second layer. Source/drain regions (52) are formed in the semiconductor layer on opposing sides of the gate stack. The gate stack is heated after the step of implanting to cause the gate stack to exert stress in the semiconductor layer in a region under the gate stack.
摘要翻译： 半导体器件（10）形成在半导体层（12）中。 在半导体层之上形成栅堆叠（16,18），并且包括第一层上的第一导电层（22）和第二层（24）。 第一层比第二层更具导电性并且为植入物提供更多的停止力。 物种（46）被植入第二层。 源极/漏极区域（52）形成在栅极堆叠的相对侧上的半导体层中。 栅极堆叠在注入步骤之后被加热，以使栅极堆叠在栅叠层下方的区域中的半导体层中施加应力。
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26.发明授权公开(公告)号：US07957190B2
公开(公告)日：2011-06-07
申请号：US12130197
申请日：2008-05-30
IPC分类号： G11C16/04
CPC分类号： G11C16/0425
摘要： A memory comprising a plurality of P-channel split-gate memory cells are organized in rows and columns. Each of the plurality of P-channel split-gate memory cells comprises a select gate, a control gate, a source region, a drain region, a channel region, and a charge storage layer comprising nanocrystals. Programming a memory cell of the plurality of P-channel split-gate memory cells comprises injecting electrons from a channel region of the memory cell to the charge storage layer. Erasing the memory cell comprises injecting holes from the channel region to the charge storage region.
摘要翻译： 包括多个P沟道分裂门存储器单元的存储器以行和列组织。 多个P沟道分离栅极存储单元中的每一个包括选择栅极，控制栅极，源极区域，漏极区域，沟道区域和包含纳米晶体的电荷存储层。 编程多个P沟道分离栅极存储单元的存储单元包括将电子从存储单元的沟道区域注入电荷存储层。 擦除存储单元包括从通道区域向电荷存储区域注入空穴。
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27.发明授权Electronic device including a transistor structure having an active region adjacent to a stressor layer 有权电子器件包括具有与应力层相邻的有源区的晶体管结构公开(公告)号：US07714318B2
公开(公告)日：2010-05-11
申请号：US12180818
申请日：2008-07-28
IPC分类号： H01L29/06
CPC分类号： H01L21/84 , H01L21/823412 , H01L21/823481 , H01L21/823807 , H01L21/823878 , H01L27/1203 , H01L29/045 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/7843
摘要： An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and the first stress type may be tensile, or the transistor structure may be an n-channel transistor structure and the first stress type may be compressive. The transistor structure can include a channel region that lies within an active region. An edge of the active region includes the interface between the channel region and the field isolation region. From a top view, the layer can include an edge the lies near the edge of the active region. The positional relationship between the edges can affect carrier mobility within the channel region of the transistor structure.
摘要翻译： 电子器件可以包括第一导电类型的晶体管结构，场隔离区域和覆盖场隔离区域的第一应力类型的层。 例如，晶体管结构可以是p沟道晶体管结构，并且第一应力类型可以是拉伸的，或者晶体管结构可以是n沟道晶体管结构，并且第一应力类型可以是压缩的。 晶体管结构可以包括位于有源区内的沟道区。 有源区域的边缘包括沟道区域和场隔离区域之间的界面。 从顶视图，该层可以包括位于活动区域边缘附近的边缘。 边缘之间的位置关系可以影响晶体管结构的沟道区内的载流子迁移率。
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28.发明申请公开(公告)号：US20090296491A1
公开(公告)日：2009-12-03
申请号：US12130197
申请日：2008-05-30
IPC分类号： G11C16/06
CPC分类号： G11C16/0425
摘要： A memory comprising a plurality of P-channel split-gate memory cells are organized in rows and columns. Each of the plurality of P-channel split-gate memory cells comprises a select gate, a control gate, a source region, a drain region, a channel region, and a charge storage layer comprising nanocrystals. Programming a memory cell of the plurality of P-channel split-gate memory cells comprises injecting electrons from a channel region of the memory cell to the charge storage layer. Erasing the memory cell comprises injecting holes from the channel region to the charge storage region.
摘要翻译： 包括多个P沟道分裂门存储器单元的存储器以行和列组织。 多个P沟道分离栅极存储单元中的每一个包括选择栅极，控制栅极，源极区域，漏极区域，沟道区域和包含纳米晶体的电荷存储层。 编程多个P沟道分离栅极存储单元的存储单元包括将电子从存储单元的沟道区域注入电荷存储层。 擦除存储单元包括从通道区域向电荷存储区域注入空穴。
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公开(公告)号：US07572706B2
公开(公告)日：2009-08-11
申请号：US11680181
申请日：2007-02-28
申请人： Da Zhang , Brian A. Winstead
发明人： Da Zhang , Brian A. Winstead
IPC分类号： H01L21/336 , H01L21/8236
CPC分类号： H01L29/66628 , H01L21/26586 , H01L29/665 , H01L29/6656 , H01L29/66621 , H01L29/66636 , H01L29/66659 , H01L29/66772 , H01L29/7835 , H01L29/7848
摘要： A method for forming a semiconductor device is provided. The method includes forming a gate structure overlying a substrate. The method further includes forming a sidewall spacer adjacent to the gate structure. The method further includes performing an angled implant in a direction of a source side of the semiconductor device. The method further includes annealing the semiconductor device. The method further includes forming recesses adjacent opposite ends of the sidewall spacer in the substrate to expose a first type of semiconductor material. The method further includes epitaxially growing a second type of semiconductor material in the recesses, wherein the second type of semiconductor material has a lattice constant different from a lattice constant of the first type of semiconductor material to create stress in a channel region of the semiconductor device.
摘要翻译： 提供一种形成半导体器件的方法。 该方法包括形成覆盖衬底的栅极结构。 该方法还包括形成邻近栅极结构的侧壁间隔物。 该方法还包括在半导体器件的源极侧的方向上执行成角度的注入。 该方法还包括退火半导体器件。 该方法还包括在衬底中的侧壁间隔物的相对端附近形成凹部以暴露第一类型的半导体材料。 该方法还包括在凹槽中外延生长第二类型的半导体材料，其中第二类型的半导体材料具有不同于第一类型的半导体材料的晶格常数的晶格常数，以在半导体器件的沟道区域中产生应力 。
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公开(公告)号：US07479422B2
公开(公告)日：2009-01-20
申请号：US11373536
申请日：2006-03-10
申请人： Brian A. Winstead , Ted R. White , Da Zhang
发明人： Brian A. Winstead , Ted R. White , Da Zhang
IPC分类号： H01L21/336
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A method for forming a semiconductor device includes providing a substrate region having a first material and a second material overlying the first material, wherein the first material has a different lattice constant from a lattice constant of the second material. The method further includes etching a first opening on a first side of a gate and etching a second opening on a second side of the gate. The method further includes creating a first in-situ p-type doped epitaxial region in the first opening and the second opening, wherein the first in-situ doped epitaxial region is created using the second material. The method further includes creating a second in-situ n-type doped expitaxial region overlying the first in-situ p-type doped epitaxial region in the first opening and the second opening, wherein the second in-situ n-type doped epitaxial region is created using the second material.
摘要翻译： 一种形成半导体器件的方法包括提供具有第一材料和覆盖第一材料的第二材料的衬底区域，其中第一材料具有与第二材料的晶格常数不同的晶格常数。 该方法还包括蚀刻栅极的第一侧上的第一开口并蚀刻栅极的第二侧上的第二开口。 该方法还包括在第一开口和第二开口中产生第一原位p型掺杂外延区域，其中使用第二材料产生第一原位掺杂外延区域。 该方法还包括在第一开口和第二开口中形成覆盖第一原位p型掺杂外延区域的第二原位n型掺杂截留区域，其中第二原位n型掺杂外延区域是 使用第二种材料创建。
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