公开(公告)号：US20070189103A1

公开(公告)日：2007-08-16

申请号：US11355802

申请日：2006-02-16

申请人： James Johnson ,  Feng Lin ,  Brent Keeth

发明人： James Johnson ,  Feng Lin ,  Brent Keeth

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C29/50 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C11/401 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012

摘要： A method and circuitry for improved write latency tracking in a SDRAM is disclosed. In one embodiment, a delay locked loop is used in the command portion of the write path, and receives the system clock as its reference input. The DLL includes a modeled delay which models the delay in transmission of the internal Write Valid signal and system clock distribution to the deserializers in the data path portion of the write path, which is otherwise controlled by the intermittently asserted write strobe signal. With the input distribution delay of the system clock (Clk) and the write strobe (WS) matched by design, the distributed system clock and Write Valid signal are synchronized to the WS distribution path by means of the DLL delay with reference to the system clock input to the DLL. By backing the distribution delay out of system clock as sent to the deserializers, the write valid signal is effectively synchronized with the write strobe, with the effect that data will be passed out of the deserializer circuitry to the memory array on time and consistent with the programmed write latency.

摘要翻译： 公开了一种用于在SDRAM中改进写延迟跟踪的方法和电路。 在一个实施例中，在写入路径的命令部分中使用延迟锁定环，并且接收系统时钟作为其参考输入。 DLL包括建模延迟，其将内部写入有效信号的传输延迟和系统时钟分布建模到写入路径的数据路径部分中的解串行器，否则由间歇性断言的写入选通信号控制。 随着系统时钟（Clk）的输入分配延迟和设计匹配的写选通（WS），分布式系统时钟和写有效信号通过参考系统时钟的DLL延迟与WS分配路径同步 输入到DLL。 通过将分发延迟从发送到解串器的系统时钟中提取出来，写入有效信号与写入选通有效地同步，其影响是数据将及时从解串器电路传送到存储器阵列，并与 编程写延迟。

公开(公告)号：US07221201B2

公开(公告)日：2007-05-22

申请号：US10915774

申请日：2004-08-11

申请人： Feng Lin ,  Brent Keeth

发明人： Feng Lin ,  Brent Keeth

IPC分类号： H03L7/06

CPC分类号： H03L7/10 ,  H03L7/0814

摘要： A method and apparatus for synchronizing signals. For devices, such as memory devices, implementing a synchronization device to synchronize signals, a synchronization device having a delay locked loop coupled to a phase locked loop may be implemented. The delay locked loop is implemented to measure the period of a reference signal and to mirror the period into a second delay line such that an adjusted reference signal having a frequency approximately equal to the frequency of the reference clock may be generated. The adjusted reference signal is delivered to an oscillator such that the oscillator begins oscillating at approximately the same frequency as the reference clock signal to provide a fast locking synchronization device.

摘要翻译： 一种用于同步信号的方法和装置。 对于诸如存储设备的设备，实现同步设备来同步信号，可以实现具有耦合到锁相环路的延迟锁定环路的同步设备。 执行延迟锁定环路以测量参考信号的周期并将周期镜像成第二延迟线，使得可以生成具有近似等于参考时钟的频率的频率的经调整的参考信号。 调整的参考信号被传送到振荡器，使得振荡器以与参考时钟信号大致相同的频率开始振荡，以提供快速锁定同步装置。

公开(公告)号：US20060202726A1

公开(公告)日：2006-09-14

申请号：US11388226

申请日：2006-03-23

申请人： Feng Lin ,  Brent Keeth

发明人： Feng Lin ,  Brent Keeth

IPC分类号： H03L7/00

CPC分类号： H03L7/10 ,  H03L7/0814

摘要： An apparatus for synchronizing signals. For devices, such as memory devices, implementing a synchronization device to synchronize signals, a synchronization device having a delay locked loop coupled to a phase locked loop may be implemented. The delay locked loop is implemented to measure the period of a reference signal and to mirror the period into a second delay line such that an adjusted reference signal having a frequency approximately equal to the frequency of the reference clock may be generated. The adjusted reference signal is delivered to an oscillator such that the oscillator begins oscillating at approximately the same frequency as the reference clock signal to provide a fast locking synchronization device.

摘要翻译： 一种用于同步信号的装置。 对于诸如存储设备的设备，实现同步设备来同步信号，可以实现具有耦合到锁相环路的延迟锁定环路的同步设备。 执行延迟锁定环路以测量参考信号的周期并将周期镜像成第二延迟线，使得可以生成具有近似等于参考时钟的频率的频率的经调整的参考信号。 调整的参考信号被传送到振荡器，使得振荡器以与参考时钟信号大致相同的频率开始振荡，以提供快速锁定同步装置。

公开(公告)号：US20060033542A1

公开(公告)日：2006-02-16

申请号：US10915774

申请日：2004-08-11

申请人： Feng Lin ,  Brent Keeth

发明人： Feng Lin ,  Brent Keeth

IPC分类号： H03L7/06

CPC分类号： H03L7/10 ,  H03L7/0814

摘要： A method and apparatus for synchronizing signals. For devices, such as memory devices, implementing a synchronization device to synchronize signals, a synchronization device having a delay locked loop coupled to a phase locked loop may be implemented. The delay locked loop is implemented to measure the period of a reference signal and to mirror the period into a second delay line such that an adjusted reference signal having a frequency approximately equal to the frequency of the reference clock may be generated. The adjusted reference signal is delivered to an oscillator such that the oscillator begins oscillating at approximately the same frequency as the reference clock signal to provide a fast locking synchronization device.

摘要翻译： 一种用于同步信号的方法和装置。 对于诸如存储设备的设备，实现同步设备来同步信号，可以实现具有耦合到锁相环路的延迟锁定环路的同步设备。 执行延迟锁定环路以测量参考信号的周期并将周期镜像成第二延迟线，使得可以生成具有近似等于参考时钟的频率的频率的经调整的参考信号。 调整的参考信号被传送到振荡器，使得振荡器以与参考时钟信号大致相同的频率开始振荡，以提供快速锁定同步装置。

公开(公告)号：US20090141571A1

公开(公告)日：2009-06-04

申请号：US12329779

申请日：2008-12-08

申请人： James Brian Johnson ,  Brent Keeth ,  Feng Dan Lin

发明人： James Brian Johnson ,  Brent Keeth ,  Feng Dan Lin

IPC分类号： G11C7/00 ,  G11C8/18 ,  G11C8/00

CPC分类号： G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  G11C11/4072 ,  G11C11/4076 ,  G11C2207/2254 ,  H03L7/0812 ,  H03L7/095

摘要： A method of controlling the output of data from a memory device includes deriving from an external clock signal a read clock and a control clock for operating an array of storage cells, both the read clock and the control clock each being comprised of clock pulses. A value is preloaded into one or both of a first counter located in the read clock domain and a second counter located in the control clock domain such that the difference in starting counts between the two counters is equal to a column address strobe latency (L) minus a synchronization (SP) overhead. A start signal is generated for initiating production of a running count of the read clock pulses in the first counter. The input of the start signal to the second counter is delayed so as to delay the initiation of a running count of the control clock pulses. A value of the second counter is held in response to a read command. The held value of the second counter is compared to a running count of the first counter; and data is output from the memory device with the read clock signal in response to the comparing.

摘要翻译： 控制来自存储器件的数据输出的方法包括从外部时钟信号导出读时钟和用于操作存储单元阵列的控制时钟，读时钟和控制时钟均由时钟脉冲组成。 值被预加载到位于读时钟域中的第一计数器中的一个或两者，位于控制时钟域中的第二计数器，使得两个计数器之间的启动计数的差值等于列地址选通延迟（L） 减去同步（SP）开销。 产生起始信号，用于开始产生第一计数器中的读取时钟脉冲的运行计数。 启动信号到第二计数器的输入被延迟，以延迟启动控制时钟脉冲的运行计数。 响应于读取命令来保持第二计数器的值。 将第二计数器的保持值与第一计数器的运行计数进行比较; 并且响应于比较，从存储器件输出具有读时钟信号的数据。

公开(公告)号：US07480203B2

公开(公告)日：2009-01-20

申请号：US12072109

申请日：2008-02-22

申请人： James Brian Johnson ,  Brent Keeth ,  Feng (Dan) Lin

发明人： James Brian Johnson ,  Brent Keeth ,  Feng (Dan) Lin

IPC分类号： G11C8/00 ,  H03L7/06

CPC分类号： G11C11/4076 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4072 ,  G11C2207/2254 ,  H03L7/0812 ,  H03L7/095

摘要： A method of synchronizing counters in two different clock domains within a memory device is comprised of generating a start signal for initiating production of a running count of clock pulses of a read clock signal in a first counter downstream of a locked loop and delaying the input of the start signal to a second counter upstream of the locked loop to delay the initiation of a running count of control clock pulses by an amount equal to a predetermined delay. Another disclosed method is for controlling the output of data from a memory device comprising deriving from an external clock signal a control clock for operating an array of storage cells and a read clock, both the control clock and the read clock being comprised of clock pulses. A start signal is generated for initiating production of a running count of the read clock pulses in a first counter. The start signal may be produced when a locked loop achieves a lock between the read clock and the control clock. The input of the start signal to a second counter is delayed to delay the initiation of a running count of the control clock pulses. The delay, which may be expressed as an integer number of clock cycles, may be equal to an input/output delay of the memory device. The method may be modified by inputting the start signal to an offset counter before initiating the production of the running count of the read clock pulses in the first counter. The offset counter may be loaded with a value equal to a programmed latency less a synchronization overhead. Once the running counts are initiated, each time a read command is received, a then current value of the running count of control clock pulses from the second counter is latched or held. The held value is compared to the running count of read clock pulses from the first counter, with the read clock signal being used to output data in response to the comparison. Apparatus for implementing the disclosed methods are also disclosed. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

公开(公告)号：US20080089158A1

公开(公告)日：2008-04-17

申请号：US11999383

申请日：2007-12-04

申请人： Brent Keeth ,  Brian Johnson ,  Troy Manning

发明人： Brent Keeth ,  Brian Johnson ,  Troy Manning

IPC分类号： G11C7/00

CPC分类号： G11C7/1072 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1078 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/107

摘要： A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

摘要翻译： 存储器件可以在高模式或低速模式下操作。 在任一模式中，来自两个存储器阵列中的每一个的32位数据被预取到相应的32个触发器组中。 在高速模式下，预取数据位并行传输到4个并行到串行转换器，它们将并行数据位转换为8个串行数据位的脉冲串，并将该脉冲串应用于4个数据总线 终端。 在低速模式下，两组预取数据位并行传送到8个并行到串行转换器，它们将并行数据位转换为8个串行数据位的脉冲串，并将该脉冲串应用于8个数据中的相应一个 巴士总站。

公开(公告)号：US07355922B2

公开(公告)日：2008-04-08

申请号：US11429856

申请日：2006-05-08

申请人： James Brian Johnson ,  Brent Keeth ,  Feng (Dan) Lin

发明人： James Brian Johnson ,  Brent Keeth ,  Feng (Dan) Lin

IPC分类号： G11C8/00 ,  H03L7/06

CPC分类号： G11C11/4076 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4072 ,  G11C2207/2254 ,  H03L7/0812 ,  H03L7/095

摘要： A method of synchronizing counters in two different clock domains within a memory device is comprised of generating a start signal for initiating production of a running count of clock pulses of a read clock signal in a first counter downstream of a locked loop and delaying the input of the start signal to a second counter upstream of the locked loop to delay the initiation of a running count of control clock pulses by an amount equal to a predetermined delay. Another disclosed method is for controlling the output of data from a memory device comprising deriving from an external clock signal a control clock for operating an array of storage cells and a read clock, both the control clock and the read clock being comprised of clock pulses. A start signal is generated for initiating production of a running count of the read clock pulses in a first counter. The start signal may be produced when a locked loop achieves a lock between the read clock and the control clock. The input of the start signal to a second counter is delayed to delay the initiation of a running count of the control clock pulses. The delay, which may be expressed as an integer number of clock cycles, may be equal to an input/output delay of the memory device. The method may be modified by inputting the start signal to an offset counter before initiating the production of the running count of the read clock pulses in the first counter. The offset counter may be loaded with a value equal to a programmed latency less a synchronization overhead. Once the running counts are initiated, each time a read command is received, a then current value of the running count of control clock pulses from the second counter is latched or held. The held value is compared to the running count of read clock pulses from the first counter, with the read clock signal being used to output data in response to the comparison. Apparatus for implementing the disclosed methods are also disclosed. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

公开(公告)号：US20060045206A1

公开(公告)日：2006-03-02

申请号：US10930543

申请日：2004-08-30

申请人： Brent Keeth ,  Joo Choi ,  George Pax ,  Ronnie Harrison ,  David Ovard ,  Dragos Dimitriu ,  Troy Manning ,  Roy Greeff ,  Greg King ,  Brian Johnson

发明人： Brent Keeth ,  Joo Choi ,  George Pax ,  Ronnie Harrison ,  David Ovard ,  Dragos Dimitriu ,  Troy Manning ,  Roy Greeff ,  Greg King ,  Brian Johnson

IPC分类号： H04L27/06

CPC分类号： H04L25/062

摘要： A method and system for generating a reference voltage for memory device signal receivers operates in either a calibration mode or a normal operating mode. In the calibration mode, the magnitude of the reference voltage is incrementally varied, and a digital signal pattern is coupled to the receiver at each reference voltage. An output of the receiver is analyzed to determine if the receiver can accurately pass the signal pattern at each reference voltage level. A range of reference voltages that allow the receiver to accurately pass the signal pattern is recorded, and a final reference voltage is calculated at the approximate midpoint of the range. This final reference voltage is applied to the receiver during normal operation.

公开(公告)号：US06697297B2

公开(公告)日：2004-02-24

申请号：US10230673

申请日：2002-08-29

申请人： Brent Keeth ,  Brian Johnson

发明人： Brent Keeth ,  Brian Johnson

IPC分类号： G11C800

CPC分类号： G11C7/109 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/409

摘要： A system and memory including a circuit for setting write latency and a write/valid indicator. Time margin regions are established just after the first or leading edge and just before the second or following edge of the preamble of the clock signal such that a latency setting will be found unacceptable if it causes a write enable signal to transition in either of these regions. A write/valid indicator circuit creates the start and end time margin regions by delaying either the clock signal or the write enable signal and comparing their timing with the timing of the undelayed write enable signal or clock signal respectively.

摘要翻译： 包括用于设置写延迟的电路和写/有效指示符的系统和存储器。 时间裕度区域刚好在第一或前沿之后并且恰好在时钟信号的前导码的第二或后沿之后建立，使得等待时间设置将被发现是不可接受的，如果其引起写入使能信号在这些区域中的任一个中转变 。 写入/有效指示电路通过延迟时钟信号或写入使能信号并分别将它们的定时与未延迟写入使能信号或时钟信号的定时进行比较来创建起始和结束时间余量区域。