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    On-chip sampling circuit and method
    1.
    发明授权
    On-chip sampling circuit and method 失效
    片上采样电路及方法

    公开(公告)号：US07404124B2

    公开(公告)日：2008-07-22

    申请号：US11712040

    申请日：2007-02-28

    申请人： Chris Martin ,  James Brian Johnson ,  Troy Manning ,  Brent Keeth

    发明人： Chris Martin ,  James Brian Johnson ,  Troy Manning ,  Brent Keeth

    IPC分类号： G01R31/28

    CPC分类号： G11C29/48 ,  G11C29/1201

    摘要： Through addressing circuitry, a sampling circuit can choose a unique internal node/signal on an encapsulated/packaged chip to be output to one or more drivers. The chosen signals available at the target node are directed either through a select circuit to an output pin, or directly to an output pin. In a preferred mode, decode circuits used to select a unique node are serially connected, allowing for a large number of signals to be made available for analyzing without a large impact on circuit layout. Because of the rules related to abstracts, this abstract should not be used in the construction of the claims.

    摘要翻译： 通过寻址电路，采样电路可以在封装/封装的芯片上选择唯一的内部节点/信号，以输出到一个或多个驱动器。 在目标节点处可用的选定信号通过选择电路指向输出引脚，或直接指向输出引脚。 在优选模式中，用于选择唯一节点的解码电路串联连接，允许大量的信号可用于分析，而不会对电路布局造成很大影响。 由于与摘要相关的规则，本摘要不应用于索赔的构建。

    Memory device and method having data path with multiple prefetch I/O configurations
    3.
    发明申请
    Memory device and method having data path with multiple prefetch I/O configurations 失效
    具有多个预取I / O配置的数据路径的存储器件和方法

    公开(公告)号：US20080089158A1

    公开(公告)日：2008-04-17

    申请号：US11999383

    申请日：2007-12-04

    申请人： Brent Keeth ,  Brian Johnson ,  Troy Manning

    发明人： Brent Keeth ,  Brian Johnson ,  Troy Manning

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1072 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1078 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/107

    摘要： A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

    摘要翻译： 存储器件可以在高模式或低速模式下操作。 在任一模式中，来自两个存储器阵列中的每一个的32位数据被预取到相应的32个触发器组中。 在高速模式下，预取数据位并行传输到4个并行到串行转换器，它们将并行数据位转换为8个串行数据位的脉冲串，并将该脉冲串应用于4个数据总线 终端。 在低速模式下，两组预取数据位并行传送到8个并行到串行转换器，它们将并行数据位转换为8个串行数据位的脉冲串，并将该脉冲串应用于8个数据中的相应一个 巴士总站。

    Memory device and method having data path with multiple prefetch I/O configurations
    5.
    发明申请
    Memory device and method having data path with multiple prefetch I/O configurations 失效
    具有多个预取I / O配置的数据路径的存储器件和方法

    公开(公告)号：US20050122789A1

    公开(公告)日：2005-06-09

    申请号：US11031437

    申请日：2005-01-07

    申请人： Brent Keeth ,  Brian Johnson ,  Troy Manning

    发明人： Brent Keeth ,  Brian Johnson ,  Troy Manning

    IPC分类号： G11C11/409 ,  G11C7/10 ,  G11C11/407 ,  G11C11/4096 ,  G11C5/00

    CPC分类号： G11C7/1072 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1078 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/107

    摘要： A memory device is operable in either a high mode or a low speed mode. In either mode 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

    摘要翻译： 存储器件可以在高模式或低速模式下操作。 在任一模式中，来自两个存储器阵列中的每一个的32位数据被预取到相应的32个触发器组中。 在高速模式下，预取数据位并行传输到4个并行到串行转换器，它们将并行数据位转换为8个串行数据位的脉冲串，并将该脉冲串应用于4个数据总线 终端。 在低速模式下，两组预取数据位并行传送到8个并行到串行转换器，它们将并行数据位转换为8个串行数据位的脉冲串，并将该脉冲串应用于8个数据中的相应一个 巴士总站。

    Multi-mode synchronous memory device and methods of operating and testing same
    6.
    发明申请
    Multi-mode synchronous memory device and methods of operating and testing same 失效
    多模同步存储器件及其操作和测试方法相同

    公开(公告)号：US20050094432A1

    公开(公告)日：2005-05-05

    申请号：US11001231

    申请日：2004-12-01

    申请人： Brian Johnson ,  Brent Keeth ,  Jeffery Janzen ,  Troy Manning ,  Chris Martin

    发明人： Brian Johnson ,  Brent Keeth ,  Jeffery Janzen ,  Troy Manning ,  Chris Martin

    IPC分类号： G01R31/28 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  G11C29/14 ,  G11C11/00

    CPC分类号： G11C29/12015 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/22 ,  G11C7/222 ,  G11C29/14

    摘要： A synchronous semiconductor memory device is operable in a normal mode and an alternative mode. The semiconductor device has a command bus for receiving a plurality of synchronously captured input signals, and a plurality of asynchronous input terminals for receiving a plurality of asynchronous input signals. The device further has a clock input for receiving an external clock signal thereon, with the device being specified by the manufacturer to be operated in the normal mode using an external clock signal having a frequency no less than a predetermined minimum frequency. An internal delay locked loop (DLL) clocking circuit is coupled to the clock input terminal and is responsive in normal operating mode to be responsive to the external clock signal to generate at least one internal clock signal. control circuitry in the device is responsive to a predetermined sequence of asynchronous signals applied to the device's asynchronous input terminals to place the device in an alternative mode of operation in which the internal clocking circuit is disabled, such that the device may be operated in the alternative mode using an external clock signal having a frequency less than the predetermined minimum frequency. The alternative mode of operation facilitates testing of the device at a speed less than the minimum frequency specified for the normal mode of operation.

    摘要翻译： 同步半导体存储器件可以在正常模式和替代模式下操作。 半导体器件具有用于接收多个同步捕获的输入信号的命令总线和用于接收多个异步输入信号的多个异步输入端子。 该装置还具有用于在其上接收外部时钟信号的时钟输入，该装置由制造商指定为使用具有不小于预定最小频率的频率的外部时钟信号在正常模式下操作。 内部延迟锁定环（DLL）时钟电路耦合到时钟输入端并且在正常操作模式下响应于外部时钟信号响应以产生至少一个内部时钟信号。 设备中的控制电路响应于施加到设备的异步输入端子的预定的异步信号序列，以将设备置于其中内部时钟电路被禁用的替代操作模式，使得该设备可以以替代方式操作 模式使用具有小于预定最小频率的频率的外部时钟信号。 替代的操作模式便于以低于为正常操作模式指定的最小频率的速度测试设备。

    On-chip sampling circuit and method
    7.
    发明授权
    On-chip sampling circuit and method 失效

    公开(公告)号：US07412634B2

    公开(公告)日：2008-08-12

    申请号：US11712041

    申请日：2007-02-28

    申请人： Chris Martin ,  James Brian Johnson ,  Troy Manning ,  Brent Keeth

    发明人： Chris Martin ,  James Brian Johnson ,  Troy Manning ,  Brent Keeth

    IPC分类号： G01R31/28

    CPC分类号： G11C29/48 ,  G11C29/1201

    摘要： Through addressing circuitry, a sampling circuit can choose a unique internal node/signal on an encapsulated/packaged chip to be output to one or more drivers. The chosen signals available at the target node are directed either through a select circuit to an output pin, or directly to an output pin. In a preferred mode, decode circuits used to select a unique node are serially connected, allowing for a large number of signals to be made available for analyzing without a large impact on circuit layout. Because of the rules related to abstracts, this abstract should not be used in the construction of the claims.

    On-chip sampling circuit and method
    8.
    发明授权
    On-chip sampling circuit and method 有权
    片上采样电路及方法

    公开(公告)号：US07251762B2

    公开(公告)日：2007-07-31

    申请号：US11109535

    申请日：2005-04-19

    申请人： Chris Martin ,  James Brian Johnson ,  Troy Manning ,  Brent Keeth

    发明人： Chris Martin ,  James Brian Johnson ,  Troy Manning ,  Brent Keeth

    IPC分类号： G01R31/28

    CPC分类号： G11C29/48 ,  G11C29/1201

    摘要： Through addressing circuitry, a sampling circuit can choose a unique internal node/signal on an encapsulated/packaged chip to be output to one or more drivers. The chosen signals available at the target node are directed either through a select circuit to an output pin, or directly to an output pin. In a preferred mode, decode circuits used to select a unique node are serially connected, allowing for a large number of signals to be made available for analyzing without a large impact on circuit layout.

    摘要翻译： 通过寻址电路，采样电路可以在封装/封装的芯片上选择唯一的内部节点/信号，以输出到一个或多个驱动器。 在目标节点处可用的选定信号通过选择电路指向输出引脚，或直接指向输出引脚。 在优选模式中，用于选择唯一节点的解码电路串联连接，允许大量的信号可用于分析，而不会对电路布局造成很大影响。

    Memory device and method having data path with multiple prefetch I/O configurations
    9.
    发明申请
    Memory device and method having data path with multiple prefetch I/O configurations 有权
    具有多个预取I / O配置的数据路径的存储器件和方法

    公开(公告)号：US20070058469A1

    公开(公告)日：2007-03-15

    申请号：US11595515

    申请日：2006-11-08

    申请人： Brent Keeth ,  Brian Johnson ,  Troy Manning

    发明人： Brent Keeth ,  Brian Johnson ,  Troy Manning

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1072 ,  G11C7/1006 ,  G11C7/1018 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1078 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/107

    摘要： A memory device is operable in either a high mode or a low speed mode. In either mode 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

    摘要翻译： 存储器件可以在高模式或低速模式下操作。 在任一模式中，来自两个存储器阵列中的每一个的32位数据被预取到相应的32个触发器组中。 在高速模式下，预取数据位并行传输到4个并行到串行转换器，它们将并行数据位转换为8个串行数据位的脉冲串，并将该脉冲串应用于4个数据总线 终端。 在低速模式下，两组预取数据位并行传送到8个并行到串行转换器，它们将并行数据位转换为8个串行数据位的脉冲串，并将该脉冲串应用于8个数据中的相应一个 巴士总站。